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1. 发明申请

WO2021194995A1 QUANTUM BIT ARRAY 审中-公开
公开(公告)号：WO2021194995A1
公开(公告)日：2021-09-30
申请号：PCT/US2021/023534
申请日：2021-03-22
申请人： HSU, Fu-Chang , HSU, Kevin
发明人： HSU, Fu-Chang , HSU, Kevin
IPC分类号： B82Y10/00 , G06N10/00 , H01L27/18 , H01L39/221 , H01L39/228 , H03K3/38
摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

2. 发明申请

WO2020176251A1 USING A MAGNETIC JOSEPHSON JUNCTION DEVICE AS A PI INVERTER 审中-公开
公开(公告)号：WO2020176251A1
公开(公告)日：2020-09-03
申请号：PCT/US2020/017804
申请日：2020-02-11
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： AMBROSE, Thomas, F. , MURDUCK, James, M.
IPC分类号： G11C11/44 , H01L39/22 , H03K3/38 , H03K17/00 , H03K19/195
摘要： Superconducting circuits and memories that use a magnetic Josephson junction (MJJ) device as a pi inverter are disclosed. The MJJ device includes superconducting layers configured to allow a flow of a supercurrent through the MJJ device. The MJJ device further includes a magnetic layer arranged between the superconducting layers, where the magnetic layer has an associated magnetization direction, and where the first state of the MJJ device corresponds to a zero-phase of a supercurrent flowing through the MJJ device and the second state of the MJJ device corresponds to a π-phase of the supercurrent flowing through the MJJ device. In response to an application of a magnetic field, without any change in the magnetization direction of the magnetic layer, the MJJ device is configured to switch from the first state to the second state responsive to a change in a phase of the supercurrent.

3. 发明申请

WO2020050897A1 SUPERCONDUCTING MEMORY WITH JOSEPHSON PHASE-BASED TORQUE 审中-公开
公开(公告)号：WO2020050897A1
公开(公告)日：2020-03-12
申请号：PCT/US2019/038807
申请日：2019-06-25
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： NAAMAN, Ofer
IPC分类号： H03K3/38 , G11C11/44
摘要： Examples described in this disclosure relate to a memory cell with Josephson phase-based torque. In one example, a memory cell including a first inductor and a magnetic Josephson junction (MJJ) coupled to the first inductor to form a loop is provided. The MJJ may include a free magnetic layer formed above a non-magnetic layer, and a fixed magnetic layer below the non-magnetic layer. A first state of the memory cell corresponds to a first magnetization of the free magnetic layer that is parallel to a magnetization of the fixed magnetic layer and the second state of the memory cell corresponds to a second magnetization of the free magnetic layer that is anti-parallel to the magnetization of the fixed magnetic layer. The memory cell is configured to switch from the first state to the second state based on whether the MJJ is in a zero-state or a π-state.

4. 发明申请

WO2019217153A1 CURRENT DRIVER SYSTEM 审中-公开
公开(公告)号：WO2019217153A1
公开(公告)日：2019-11-14
申请号：PCT/US2019/030036
申请日：2019-04-30
申请人： NORTHROP GRUMMAN SYSTEMS CORPORATION
发明人： MILLER, Donald L. , HERR, Quentin P.
IPC分类号： H03K3/38
摘要： One example includes a current driver system. The system includes a current source configured to provide a source current to a transition node. The system also includes a Josephson latch comprising at least one Josephson junction stage. The at least one Josephson junction stage can be configured to conduct the source current from the transition node as a current-clamped bias current in a deactivated state of the Josephson latch. The Josephson latch can be configured to activate in response to the bias current and a trigger pulse to switch the at least one Josephson junction stage to a voltage state to conduct at least a portion of the source current from the transition node as an output current to a load in response to activation of the Josephson latch.

5. 发明申请

WO2018073668A1 SUM FREQUENCY GENERATOR IN MICROWAVE DOMAIN FOR QUANTUM COMMUNICATE AND COMPUTATION APPLICATIONS 审中-公开
标题翻译：用于量子通信和计算应用的微波域总和频率发生器
公开(公告)号：WO2018073668A1
公开(公告)日：2018-04-26
申请号：PCT/IB2017/055520
申请日：2017-09-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： ABDO, Baleegh
IPC分类号： H03K3/38
摘要： A technique relates to a circuit for a sum frequency generator. A first resonator is connected to a Josephson ring modulator (JRM), and the first resonator is configured to receive a first photon at a first frequency．A second resonator is connected to the JRM, and the second resonator is configured to have a first harmonic and no second harmonic. The second resonator is configured to receive a second photon at a second frequency, and the first resonator is configured to output an up-converted photon. The up-converted photon has an up-converted frequency that is a sum of the first frequency and the second frequency．
摘要翻译：一种技术涉及用于和频发生器的电路。第一谐振器连接到约瑟夫森环形调制器（JRM），并且第一谐振器被配置为接收第一频率的第一光子。第二谐振器连接到JRM，并且第二谐振器配置为具有第一谐波没有二次谐波。第二谐振器被配置为以第二频率接收第二光子，并且第一谐振器被配置为输出升频转换的光子。上变频光子具有上变频频率，该频率是第一频率和第二频率的总和。

6. 发明申请

WO2018044562A3 SUPERCONDUCTING GATE MEMORY CIRCUIT 审中-公开
公开(公告)号：WO2018044562A3
公开(公告)日：2018-03-08
申请号：PCT/US2017/046987
申请日：2017-08-15
申请人： NORTHROP GRUMMAN SYSTEMS CORPORATION
发明人： BURNETT, Randall M. , HERR, Quentin P.
IPC分类号： H03K3/38 , G11C11/44 , H03K19/195
摘要： One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.

7. 发明申请

WO2018044562A2 SUPERCONDUCTING GATE MEMORY CIRCUIT 审中-公开
标题翻译：超导栅极存储器电路
公开(公告)号：WO2018044562A2
公开(公告)日：2018-03-08
申请号：PCT/US2017/046987
申请日：2017-08-15
申请人： NORTHROP GRUMMAN SYSTEMS CORPORATION
发明人： BURNETT, Randall M. , HERR, Quentin P.
IPC分类号： H03K3/38 , G11C11/44 , H03K19/195
摘要： One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.
摘要翻译：一个实施例包括超导栅极存储器电路。该电路包括约瑟夫森D门电路，该电路被配置为响应于在写入启用输入端上提供的写入启用单通量量子（SFQ）脉冲和相应存在的输入而将数字状态设置为第一数据状态和第二数据状态之一提供在数据写入输入上的写入数据SFQ脉冲的存在或不存在。该电路还包括一个耦合到约瑟夫逊D门的存储环路。存储环路可以被配置为存储数字状态并且响应于在读使能输入上提供的读使能SFQ脉冲和在读数据输入上提供的读数据SFQ脉冲而在输出处读出数字状态。

8. 发明申请

WO2017180447A1 CLOCK DISTRIBUTION NETWORK FOR A SUPERCONDUCTING INTEGRATED CIRCUIT 审中-公开
标题翻译：超导集成电路的时钟配电网络
公开(公告)号：WO2017180447A1
公开(公告)日：2017-10-19
申请号：PCT/US2017/026473
申请日：2017-04-07
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： TALANOV, Vladimir V. , STRONG, Joshua A.
IPC分类号： H03K3/38 , H01P1/18 , G06F1/10 , H03K19/195
摘要： A superconducting integrated circuit including a clock distribution network (600) for distributing a clock signal in the superconducting integrated circuit is provided. The clock distribution network (600) may include a clock structure having unit cells, where each of the unit cells may include at least one spine and at least one stub. The at least one spine is connected to the at least one stub, where the at least one stub may further be inductively coupled to at least one superconducting element. The clock signal may have a wavelength. Each of the unit cells may be spaced apart from each other along the clock structure by a distance, where the distance may be less than one tenth of the wavelength.
摘要翻译：提供了一种包括用于在超导集成电路中分配时钟信号的时钟分配网络（600）的超导集成电路。时钟分配网络（600）可以包括具有单位单元的时钟结构，其中每个单位单元可以包括至少一个脊柱和至少一个短截线。至少一个脊柱连接到至少一个短柱，其中至少一个短柱可以进一步感应耦合到至少一个超导元件。时钟信号可以具有波长。每个单位单元可以沿着时钟结构彼此间隔开一段距离，其中该距离可以小于波长的十分之一。

9. 发明申请

WO2015050621A1 PHASE HYSTERETIC MAGNETIC JOSEPHSON JUNCTION MEMORY CELL 审中-公开
标题翻译：相位滞后磁性JOSEPHSON连接存储单元
公开(公告)号：WO2015050621A1
公开(公告)日：2015-04-09
申请号：PCT/US2014/046886
申请日：2014-07-16
申请人： NORTHROP GRUMMAN SYSTEMS CORPORATION
发明人： HERR, Anna Y. , HERR, Quentin P. , NAAMAN, Ofer
IPC分类号： G11C11/44 , B82Y10/00 , G01R33/035 , G06N99/00 , H01L27/18 , H01L39/02 , H01L39/22 , H01L39/24 , H03K3/38
CPC分类号： G11C11/44 , B82Y10/00 , G01R33/0354 , G01R33/0358 , G11C11/15 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/18 , H01L39/025 , H01L39/223
摘要： One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current and to generate a superconducting phase based on the stored digital state. The memory cell also includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current.
摘要翻译：一个实施例描述了一个存储单元。存储单元包括相滞后磁约瑟夫逊结（PHMJJ），其被配置为存储对应于二进制逻辑1状态的第一二进制逻辑状态和对应于二进制逻辑0状态的第二二进制逻辑状态之一，以响应于写入电流并且基于存储的数字状态产生超导相位。存储单元还包括具有基于PHMJJ的超导相位的临界电流的至少一个约瑟夫逊结，并且被配置为响应于读取电流提供对应于存储的数字状态的输出。

10. 发明申请

WO2023081970A1 A QUANTUM MAGNETIC FIELD RECEIVING DEVICE 审中-公开
公开(公告)号：WO2023081970A1
公开(公告)日：2023-05-19
申请号：PCT/AU2022/051343
申请日：2022-11-11
申请人： THE UNIVERSITY OF ADELAIDE , GIAZOTTO, Francesco , ATANACKOVIC, Petar, B.
发明人： TETTAMANZI, Giuseppe, Carlo , NAKONE, Isaac
IPC分类号： H01L39/02 , H01L39/22 , H03F19/00 , H03K17/92 , H03K19/195 , H03K3/38 , G01R33/035
摘要： The present invention relates to a quantum magnetic field receiving device including a superconducting quantum interference device (SQUID) or a superconducting quantum interference filter (SQIF) and an electrostatic gating circuit configured to apply electrostatic fields to Josephson Junctions of the SQUID or SQIF.

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