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51. 发明申请

WO2014105403A1 HIGH PERFORMANCE LIGHT EMITTING DIODE 审中-公开
标题翻译：高性能发光二极管
公开(公告)号：WO2014105403A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/073849
申请日：2013-12-09
申请人： INVENSAS CORPORATION
发明人： MOHAMMED, Ilyas , WANG, Liang
IPC分类号： H01L33/38 , H01L33/42
CPC分类号： H01L33/382 , H01L33/0079 , H01L33/385 , H01L33/42 , H01L33/54
摘要： High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode.
摘要翻译：具有通孔的高性能发光二极管。根据本发明的第一实施例，制品包括发光二极管。发光二极管包括多个填充的通孔，其被配置为将发光二极管的一侧上的掺杂区域连接到发光二极管的另一侧上的多个触点。填充的通孔可以包含少于发光二极管表面积的10％。

52. 发明申请

WO2014035951A1 CO-SUPPORT CIRCUIT PANEL AND MICROELECTRONIC PACKAGES 审中-公开
标题翻译：辅助电路板和微电子封装
公开(公告)号：WO2014035951A1
公开(公告)日：2014-03-06
申请号：PCT/US2013/056777
申请日：2013-08-27
申请人： INVENSAS CORPORATION
发明人： CRISP, Richard, Dewitt , HABA, Belgacem , ZOHNI, Wael
IPC分类号： H01L25/065 , H01L23/498 , H01L25/10 , G11C5/06
CPC分类号： H01L25/0652 , G11C5/063 , H01L23/49822 , H01L23/49827 , H01L23/5385 , H01L23/5389 , H01L25/0655 , H01L25/105 , H01L2924/0002 , H05K1/0298 , H05K1/111 , H05K2201/10159 , H01L2924/00
摘要： A circuit panel 720 can include contacts 760 exposed at a connection site 761 of a major surface 721 thereof and configured to be coupled to terminals 504 of a microelectronic package 500. The connection site 761 can define a peripheral boundary 764 on the major surface 721 surrounding a group of the contacts 760 that is configured to be coupled to a single microelectronic package 500. The group of contacts 760 can include first, second, third, and fourth sets AO, AO', Al ', Al of first contacts 704. Signal assignments of the first and third sets AO, Al ' of first contacts can be symmetric about a theoretical plane 532 normal to the major surface 721 with signal assignments of the respective second and fourth sets AO ', Al of first contacts. Each of the sets AO, AO', Al ', Al of first contacts 704 can be configured to carry identical signals.
摘要翻译：电路面板720可以包括暴露在其主表面721的连接位置761处并且被配置为耦合到微电子封装500的端子504的触点760.连接部位761可以在主表面721周围限定外围边界764 一组触点760被配置为耦合到单个微电子封装500.触点组760可以包括第一触头704的第一，第二，第三和第四组AO，AO'，A1'，A1。信号第一触点的第一和第三组AO，A1'的分配可以关于垂直于主表面721的理论平面532对称，其中第一触点的相应的第二和第四组AO'，A1的信号分配。第一触点704的组AO，AO'，A1'，A1中的每一个可被配置为携带相同的信号。

53. 发明申请

WO2014014811A1 METHOD OF PROCESSING A DEVICE SUBSTRATE 审中-公开
标题翻译：处理器件基片的方法
公开(公告)号：WO2014014811A1
公开(公告)日：2014-01-23
申请号：PCT/US2013/050469
申请日：2013-07-15
申请人： INVENSAS CORPORATION
发明人： MONADGEMI, Pezhman
IPC分类号： H01L21/768 , H01L21/78
CPC分类号： H01L23/562 , H01L21/304 , H01L21/31133 , H01L21/76898 , H01L21/78 , H01L2924/0002 , H01L2924/00
摘要： Methods of processing a device substrate (200) are disclosed herein. In one embodiment, a method of processing a device substrate (200) can include bonding a first surface (206) of a device substrate (200) to a carrier (302) with a polymeric material (300). The device substrate (200) may have a plurality of first openings (210) extending from the first surface (206) towards a second surface (208) of the device substrate (200) opposite from the first surface (206). Then, material can be removed at the second surface (208) of the device substrate (200), wherein at least some of the first openings (210) communicate with the second surface (208) at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material (300) disposed between the first surface (206) and the carrier substrate (302) can be exposed to a substance through at least some first openings (210) to debond the device substrate (200) from the carrier substrate (302).
摘要翻译：本文公开了处理器件衬底（200）的方法。在一个实施例中，处理器件衬底（200）的方法可以包括用聚合材料（300）将器件衬底（200）的第一表面（206）结合到载体（302）。器件衬底（200）可以具有从第一表面（206）延伸到与第一表面（206）相对的器件衬底（200）的第二表面（208）的多个第一开口（210）。然后，可以在装置基板（200）的第二表面（208）处去除材料，其中至少一些第一开口（210）在执行去除之前或之后与第二表面（208）连通的材料。然后，设置在第一表面（206）和载体衬底（302）之间的聚合物材料（300）的至少一部分可以通过至少一些第一开口（210）暴露于物质，以使器件衬底（200）脱粘）从载体衬底（302）。

54. 发明申请

WO2013177134A1 SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT 审中-公开
标题翻译：带有线束互连的基板不可堆叠封装
公开(公告)号：WO2013177134A1
公开(公告)日：2013-11-28
申请号：PCT/US2013/041981
申请日：2013-05-21
申请人： INVENSAS CORPORATION
发明人： MOHAMMED, Ilyas
IPC分类号： H01L23/00 , H01L23/538 , H01L25/10 , H01L21/48 , H01L23/495
CPC分类号： H01L23/5226 , H01L21/563 , H01L21/568 , H01L21/76877 , H01L21/76892 , H01L23/5389 , H01L24/06 , H01L24/18 , H01L24/19 , H01L24/20 , H01L24/45 , H01L24/49 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L2224/04042 , H01L2224/04105 , H01L2224/32145 , H01L2224/32245 , H01L2224/45101 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45565 , H01L2224/45624 , H01L2224/45655 , H01L2224/45664 , H01L2224/45669 , H01L2224/4569 , H01L2224/49 , H01L2224/73267 , H01L2225/06524 , H01L2225/06548 , H01L2225/06558 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/182 , H01L2924/191 , H01L2924/19107 , H05K3/4046 , H05K2201/10287 , H05K2203/1461 , H01L2224/48 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/01049
摘要： A method for making a microelectronic unit (10) includes forming wire bonds (32) on a conductive bonding surface (30') of a patternable metallic element (28'). The wire bonds are formed having bases (34) joined to the first surface and end surfaces (38) remote from the first surface. The wire bonds have edge surfaces (36) extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer (42) over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements (28) beneath the wire bonds and insulated from one another by portions of the encapsulation layer.
摘要翻译：制造微电子单元（10）的方法包括在可图案化金属元件（28'）的导电接合表面（30'）上形成引线接合（32）。线接合形成有与第一表面和远离第一表面的端面（38）接合的基部（34）。线接合具有在基部和端面之间延伸的边缘表面（36）。该方法还包括在导电层的第一表面的一部分上形成电介质封装层（42），并且在引线的部分上键合，使得引线接合的未封装部分由端表面或边缘表面的部分限定，被封装层覆盖。金属元件被图案化以在引线键合之下形成第一导电元件（28），并且通过封装层的一部分彼此绝缘。

55. 发明申请

WO2013126269A1 METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE 审中-公开
标题翻译：封装包装装配方法用线束封装表面
公开(公告)号：WO2013126269A1
公开(公告)日：2013-08-29
申请号：PCT/US2013/026126
申请日：2013-02-14
申请人： INVENSAS CORPORATION
发明人： CO, Reynaldo , MIRKARIMI, Laura
IPC分类号： H01L23/498 , H01L21/48 , H01L23/00 , H01L25/10
CPC分类号： H01L23/3128 , H01L21/4853 , H01L23/3121 , H01L23/49517 , H01L23/49811 , H01L24/03 , H01L24/06 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/81 , H01L24/85 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/49171 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2224/78301 , H01L2224/81801 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/00012 , H01L2224/32145 , H01L2924/00 , H01L2924/014 , H01L2224/05599
摘要： A microelectronic assembly (10) includes a substrate (12) having a first and second opposed surfaces. A microelectronic element (22) overlies the first surface and first electrically conductive elements (28) can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements (28) are electrically connected to the microelectronic element (22). Wire bonds (32) have bases (34) joined to the conductive elements (28) and end surfaces (38) remote from the substrate and the bases, each wire bond defining an edge surface (37) extending between the base and the end surface. An encapsulation layer (42) can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds (32) are defined by at least portions of the end surfaces (38) of the wire bonds that are uncovered by the encapsulation layer (42).
摘要翻译：微电子组件（10）包括具有第一和第二相对表面的衬底（12）。微电子元件（22）覆盖在第一表面上，并且第一导电元件（28）可以在第一表面或第二表面中的至少一个处露出。一些第一导电元件（28）电连接到微电子元件（22）。线接合（32）具有接合到导电元件（28）和远离基板和基座的端表面（38）的基部（34），每个引线接合限定在基部和端面之间延伸的边缘表面（37）。封装层（42）可以从第一表面延伸并填充引线键合之间的空间，使得引线键合可以被封装层分离。线接合（32）的未封装的部分由未被封装层（42）覆盖的引线接合的端面（38）的至少一部分限定。

56. 发明申请

WO2013106288A1 OPTICAL INTERPOSER 审中-公开
标题翻译：光学插件
公开(公告)号：WO2013106288A1
公开(公告)日：2013-07-18
申请号：PCT/US2013/020578
申请日：2013-01-07
申请人： INVENSAS CORPORATION
发明人： KOSENKO, Valentin , BCBAIN, Edward Lee , UZOH, Cyprian Emeka , MONADGEMI, Pezhman , SAVASTIOUK, Sergey
IPC分类号： G02B6/42 , G02B6/36
CPC分类号： G02B6/4214 , G02B6/3628 , G02B6/3636 , G02B6/3652 , G02B6/3692 , G02B6/4249 , Y10T29/49117
摘要： An optical interposer includes grooves (310) for optical fiber cables (104) coupled to a transducer (120). The grooves are formed by etching a cavity (410) in a substrate (130), filling the cavity with some layer (520), then etching the layer to form the grooves. The cavity has outwardly sloped sidewalls on which mirrors (144) are later formed. The groove etch is selective not to damage the sidewalls. The groove depth is uniform due to high etch selectivity of the layer, and also because of good control over the cavity etch due to the low aspect ratio of the cavity. Electrical circuitry for connection to the transducer is fabricated after the cavity filling but before the groove etch. The cavity filling leaves the wafer planar, facilitating fabrication of the electrical circuitry. Grooves can be provided on top and bottom of the interposer.
摘要翻译：光学插入器包括耦合到换能器（120）的光纤电缆（104）的凹槽（310）。凹槽通过蚀刻衬底（130）中的空腔（410）形成，用一些层（520）填充空腔，然后蚀刻该层以形成凹槽。空腔具有向外倾斜的侧壁，后面形成有反射镜（144）。凹槽蚀刻是选择性的，不损坏侧壁。由于该层的高蚀刻选择性，凹槽深度是均匀的，并且还由于腔的低纵横比由于对腔蚀刻的良好控制。用于连接到换能器的电路在腔填充之后但在凹槽蚀刻之前制造。空腔填充离开晶片平面，便于制造电路。可以在插入器的顶部和底部提供凹槽。

57. 发明申请

WO2013106173A1 STACKABLE MICROELECTRONIC PACKAGE STRUCTURES 审中-公开
标题翻译：堆叠微电子封装结构
公开(公告)号：WO2013106173A1
公开(公告)日：2013-07-18
申请号：PCT/US2012/070477
申请日：2012-12-19
申请人： INVENSAS CORPORATION
发明人： HABA, Belgacem , BANG, Kyong-mo
IPC分类号： H01L25/10 , H01L23/538 , H01L25/065 , H01L23/34
CPC分类号： H01L25/0655 , B81C1/00301 , H01L23/13 , H01L23/3107 , H01L23/3128 , H01L23/367 , H01L24/13 , H01L24/16 , H01L24/20 , H01L24/48 , H01L24/49 , H01L24/96 , H01L25/0652 , H01L25/105 , H01L2224/12105 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/221 , H01L2224/48091 , H01L2224/48106 , H01L2224/48228 , H01L2224/4824 , H01L2224/49109 , H01L2224/4911 , H01L2224/96 , H01L2225/0651 , H01L2225/0652 , H01L2225/06524 , H01L2225/06548 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/18165 , H01L2924/19107 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A microelectronic assembly (8) includes a first microelectronic package (10A) having a substrate (12) with first (14) and second (16) surfaces and substrate contacts (24). The first package further includes first and second microelectronic elements (40) having element contacts electrically connected with the substrate contacts (24) and spaced apart from one another on the first surface to provide an interconnect area between the first and second microelectronic elements. A plurality of package terminals (74) at the second surface are interconnected with the substrate contacts for connecting the package with an external component. A plurality of stack terminals (28) are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package (10B) overlying the first microelectronic package and having terminals (62) joined to the stack terminals of the first microelectronic package.
摘要翻译：微电子组件（8）包括具有第一（14）和第二（16）表面的衬底（12）和衬底触点（24）的第一微电子封装（10A）。第一封装还包括第一和第二微电子元件（40），元件触点与衬底触点（24）电连接并且在第一表面上彼此间隔开，以在第一和第二微电子元件之间提供互连区域。在第二表面处的多个封装端子（74）与用于将封装件与外部部件连接的基板触点互连。多个堆叠端子（28）在互连区域的第一表面处露出，用于将封装与覆盖在基板的第一表面上的部件连接。组件还包括覆盖在第一微电子封装上并具有连接到第一微电子封装的堆叠端子的端子（62）的第二微电子封装（10B）。

58. 发明申请

WO2013067270A1 BONDING WEDGE 审中-公开
标题翻译：结婚之夜
公开(公告)号：WO2013067270A1
公开(公告)日：2013-05-10
申请号：PCT/US2012/063186
申请日：2012-11-02
申请人： INVENSAS CORPORATION , MCGRATH, Scott
发明人： MCGRATH, Scott
IPC分类号： H01L21/60 , B23K20/00
CPC分类号： H01L24/43 , B23K20/004 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L24/85 , H01L2224/02166 , H01L2224/022 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05571 , H01L2224/05599 , H01L2224/0603 , H01L2224/1134 , H01L2224/29099 , H01L2224/2929 , H01L2224/29311 , H01L2224/29313 , H01L2224/29339 , H01L2224/29347 , H01L2224/32225 , H01L2224/32245 , H01L2224/43 , H01L2224/45015 , H01L2224/45099 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/4847 , H01L2224/48472 , H01L2224/73265 , H01L2224/78301 , H01L2224/78313 , H01L2224/85181 , H01L2224/85186 , H01L2224/85207 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01327 , H01L2924/078 , H01L2924/00 , H01L2924/00012 , H01L2924/0665 , H01L2224/05552
摘要： A bonding wedge particularly suitable for making wire off-die interconnects includes an aperture (aperture) opening onto a notch (notch) or pocket adjacent to the rear of a foot (foot). The foot includes a heel portion (heel) and a toe portion (toe). When the bonding wedge is in use, a wire is fed from feedstock through the aperture and the notch or pocket, and passes beneath the foot and extends beyond the toe. The toe is configured to mitigate upward displacement of the free end (free end) of the wire during the bonding process.
摘要翻译：特别适用于制造线芯离线互连的接合楔包括在与脚（脚）的后部相邻的凹口（凹口）或口袋上的开口（孔）。足部包括脚跟部分（脚后跟）和脚趾部分（脚趾）。当使用结合楔时，电线通过孔和凹口或口袋从原料进料，并且在脚下方延伸并延伸超过脚趾。脚趾构造成在接合过程中减轻线的自由端（自由端）的向上位移。

59. 发明申请

WO2013052544A1 STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE 审中-公开
标题翻译：从包裹中心的终端网络的最小化
公开(公告)号：WO2013052544A1
公开(公告)日：2013-04-11
申请号：PCT/US2012/058557
申请日：2012-10-03
申请人： INVENSAS CORPORATION
发明人： CRISP, Richard Dewitt , ZOHNI, Wael
IPC分类号： H01L23/498 , H01L23/482
CPC分类号： H01L25/105 , G11C5/04 , H01L23/13 , H01L23/3128 , H01L23/4822 , H01L23/49838 , H01L23/50 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/04042 , H01L2224/05553 , H01L2224/06156 , H01L2224/06164 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2225/1052 , H01L2225/107 , H01L2924/00014 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H05K1/0243 , H05K3/3436 , H05K2201/10159 , H05K2201/10545 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package (100) includes a microelectronic element (130) having memory storage array function overlying a first surface (108) of a substrate, the microelectronic element having a plurality of contacts (132) aligned with an aperture (112) in the substrate. First terminals (104) which are configured to carry all address signals transferred to the package can be exposed within a first region (140) of a second substrate surface (110), the first region disposed between the aperture (112) and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe.
摘要翻译：微电子封装（100）包括具有覆盖衬底的第一表面（108）的存储器阵列功能的微电子元件（130），所述微电子元件具有与衬底中的孔（112）对准的多个触点（132）。配置为承载传送到包装的所有地址信号的第一端子（104）可以暴露在第二衬底表面（110）的第一区域（140）内，第一区域设置在孔（112）和外围边缘的基底。第一端子可以被配置为携带传送到封装的所有命令信号，存储体地址信号和命令信号，命令信号是写使能，行地址选通和列地址选通。

60. 发明申请

WO2013052372A2 STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS 审中-公开
标题翻译：具有平行窗口的多芯线绕组组合的最小化
公开(公告)号：WO2013052372A2
公开(公告)日：2013-04-11
申请号：PCT/US2012/057905
申请日：2012-09-28
申请人： INVENSAS CORPORATION
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
CPC分类号： G06F1/16 , G06F1/18 , G11C5/04 , G11C5/063 , G11C5/066 , H01L23/13 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/06156 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01322 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/19041 , H01L2924/19103 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package 10 can include a substrate 20 having first and second surfaces 21, 22 and first and second apertures 26a, 26b extending therebetween, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface, terminals 25a exposed at the second surface in a central region 23 thereof, and leads 40 electrically connected between contacts 35 exposed at the surface of each microelectronic element and the terminals. The apertures 26a, 26b can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 can be disposed between the first and second axes 29a, 29b. The terminals 25a can be configured to carry address information usable by circuitry within the microelectronic package 10 to determine an addressable memory location from among all the available addressable memory locations of a memory storage array of at least one of the microelectronic elements 30a, 30b.
摘要翻译：微电子封装10可以包括具有第一和第二表面21,22的衬底20和在其间延伸的第一和第二孔26a，26b，第一和第二微电子元件30a，30b，每个具有面向第一表面的表面31，在其中央区域23中的第二表面和电连接在暴露在每个微电子元件的表面处的触点35和端子之间的引线40。孔26a，26b可以具有在相应孔的长度方向上延伸的第一和第二平行轴线29a，29b。第二表面22的中心区域23可以设置在第一和第二轴线29a，29b之间。终端25a可以被配置为承载可由微电子封装10内的电路使用的地址信息，以从微电子元件30a，30b中的至少一个的存储器存储阵列的所有可寻址的存储器单元中确定可寻址的存储器位置。

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