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41. 发明申请

WO2015065786A1 MULTIPLE CHANNEL MATCHING METHOD 审中-公开
标题翻译：多通道匹配方法
公开(公告)号：WO2015065786A1
公开(公告)日：2015-05-07
申请号：PCT/US2014/061756
申请日：2014-10-22
申请人： THORLABS, INC.
发明人： GOSSAGE, Kirk
IPC分类号： H03M1/18 , H03M1/34
CPC分类号： H04N5/37455 , H04N5/3653 , H04N5/37213 , H04N5/378
摘要： A method for matching one or more channels to a reference channel in a multiple-channel detector having a digital output, the method including: receiving an analog-to-digital unit (ADU) input value from the multiple-channel detector for each channel; and replacing the ADU input value by an output value corresponding to each channel from a look up table (LUT); wherein the LUT is created by: taking a relative intensity ratio of signals from each channel compared to the reference channel over a range of voltage values; calculating a signal value on the detector that generates a specific ADU value across the entire ADU range of the detector; interpolating the relative intensity ratios to obtain ratios corresponding to the calculated signal values for each channel; and dividing the each of the specific ADU value by the corresponding interpolated ratio to obtain the corresponding output value for each channel.
摘要翻译：一种用于在具有数字输出的多通道检测器中将一个或多个通道匹配到参考通道的方法，所述方法包括：从每个通道的多通道检测器接收模数数字单元（ADU）输入值; 并且从查询表（LUT）将ADU输入值替换为对应于每个通道的输出值; 其中所述LUT是通过以下方式产生的：在一个电压值的范围内，获得与所述参考通道相比较的来自每个通道的信号的相对强度比; 计算在检测器上产生在检测器的整个ADU范围内的特定ADU值的信号值; 内插相对强度比以获得对应于每个信道的计算信号值的比率; 并且将每个特定ADU值除以相应的内插比，以获得每个通道的相应输出值。

42. 发明申请

WO2010118040A1 READOUT CIRCUIT AND SYSTEM INCLUDING SAME 审中-公开
标题翻译：读出电路和系统，包括它们
公开(公告)号：WO2010118040A1
公开(公告)日：2010-10-14
申请号：PCT/US2010/030110
申请日：2010-04-06
申请人： BRIDGE SEMICONDUCTOR CORPORATION
发明人： ACQUAVIVA, Joseph, R. , AHMED, Arif
IPC分类号： H03M1/34
CPC分类号： H04N5/33 , H04N5/378
摘要： A readout circuit. The readout circuit includes a charge amplification circuit and an analog-to-digital conversion circuit. The analog-to-digital conversion circuit is connected to the charge amplification circuit.
摘要翻译：读出电路。读出电路包括电荷放大电路和模数转换电路。模数转换电路连接到电荷放大电路。

43. 发明申请

WO2009134734A2 SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER WITH IMPROVED IMMUNITY TO TIME VARYING NOISE 审中-公开
标题翻译：具有改进的免疫功能的数字转换器的后续逼近寄存器模拟
公开(公告)号：WO2009134734A2
公开(公告)日：2009-11-05
申请号：PCT/US2009041871
申请日：2009-04-28
申请人： ANALOG DEVICES INC , MADHAVAN MAHESH , NITTALA SRIKANTH
发明人： MADHAVAN MAHESH , NITTALA SRIKANTH
IPC分类号： H03M1/34
CPC分类号： H03M1/0845 , H03M1/068 , H03M1/468
摘要： An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (VREF). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled VREFsi gnal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same VREFn oise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.
摘要翻译： SAR ADC通过在参考电位（VREF）上提供的时变噪声分量引入的噪声提高了抗干扰能力。在比特试验期间将参考电压分量引入一对二进制加权电容阵列（NDAC和PDAC）来消除参考电压噪声贡献，这些组合作为共模信号呈现给差分比较器并被拒绝。在采样期间，选择PDAC或NDAC中的元件也可以获得参考电压的贡献。虽然采样的VREFSI数据可能具有噪声贡献，但是在比特测试时，噪声是固定的，这可以提高性能。通常，该方案相对于现有技术相对于相同的VREFn oise提供的噪声误差降低了50％。本文所述的其它实施例可以将噪声误差降低到比现有技术系统的25％甚至12.5％。

44. 发明申请

WO2008094626A3 COMMON-MODE INSENSITIVE SAMPLER 审中-公开
标题翻译：共模不敏感采样器
公开(公告)号：WO2008094626A3
公开(公告)日：2008-09-25
申请号：PCT/US2008001263
申请日：2008-01-29
申请人： KENET INC , KUSHNER LAWRENCE J , ANTHONY MICHAEL P , FISHER JOHN S
发明人： KUSHNER LAWRENCE J , ANTHONY MICHAEL P , FISHER JOHN S
IPC分类号： H03M1/34
CPC分类号： H03M1/0636 , H03M1/1245
摘要： An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node 'Vcmi'. An alternative, switched-capaci tor- based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.
摘要翻译：一种在采样器/转换器中抑制输入共模电压变化的方法，避免在信号路径中使用差分放大器，并且不会引入额外的失真或噪声。在一个实施例中，在节点'Vcmi'上在跨越共模模拟输入的一对匹配电阻器上感测输入共模变化。另一种基于开关电容的感测方案也是可能的。使用这个测量的Vcmi，然后对采样器/转换器的其余部分进行调整，以取出在Vcmi处观察到的任何变化。

45. 发明申请

WO2005104377A3 A METHOD AND SYSTEM FOR ANALOG TO DIGITAL CONVERSION USING DIGITAL PULSE WIDTH MODULATION (PWM) 审中-公开
标题翻译：使用数字脉冲宽度调制（PWM）模拟数字转换的方法和系统
公开(公告)号：WO2005104377A3
公开(公告)日：2006-05-18
申请号：PCT/US2005007848
申请日：2005-03-10
申请人： MOTOROLA INC , MIDYA PALLAB , MILLER MATTHEW R , RAKERS PATRICK L
发明人： MIDYA PALLAB , MILLER MATTHEW R , RAKERS PATRICK L
IPC分类号： H03M1/34 , H03M1/12 , H03M1/50 , H03M3/02
CPC分类号： H03M3/00
摘要： A system and method for analog-to-digital conversion (118) using digital pulse width modulation (PWM) is disclosed. The method and system according to the disclosed invention converts an analog input signal (104) to a digital signal in pulse code modulated (PCM) form (106). The disclosed invention uses a feedback circuit (114) to perform PWM of the analog input signal. The PWM signal is then decimated to obtain the digital signal in PCM form. The system according to the disclosed invention requires lower operating frequency and dissipates lesser power than prior art systems providing the same sampling frequency and resolution. The operation at a lower frequency is achieved by obtaining two samples from every pulse of the PWM signal; the first sample being obtained from the right duty ratio. Further the disclosed invention has lesser implementation complexity and higher signal-to-noise ratio than prior art.
摘要翻译：公开了一种使用数字脉宽调制（PWM）的模数转换（118）的系统和方法。根据所公开的发明的方法和系统将模拟输入信号（104）转换成脉冲编码调制（PCM）形式（106）的数字信号。所公开的发明使用反馈电路（114）来执行模拟输入信号的PWM。然后抽取PWM信号以获得PCM形式的数字信号。根据所公开的发明的系统需要更低的工作频率并且消耗比提供相同采样频率和分辨率的现有技术系统更小的功率。通过从PWM信号的每个脉冲获得两个采样来实现较低频率的操作; 第一个样品是从正确的占空比中获得的。此外，所公开的发明具有比现有技术更小的实现复杂度和更高的信噪比。

46. 发明申请

WO2005004373A3 CONTINUOUS-TIME DIGITAL SIGNAL GENERATION, TRANSMISSION, STORAGE AND PROCESSING 审中-公开
标题翻译：连续数字信号的产生，传输，存储和处理
公开(公告)号：WO2005004373A3
公开(公告)日：2005-12-29
申请号：PCT/US2004020814
申请日：2004-06-28
申请人： UNIV COLUMBIA , TSIVIDIS YANNIS
发明人： TSIVIDIS YANNIS
IPC分类号： G06F7/544 , H03H17/02 , H03M1/12 , H03M1/36 , H03M1/34
CPC分类号： G06F7/5443 , H03H17/0289 , H03M1/125 , H03M1/36
摘要： A method of digitally processing an analog signal in continuous time includes producing a continuous-time digital signal from an analog signal via a technique that does not include periodic sampling, then producing one or more delayed versions of the continuous-time digital signal. Each delayed version is delayed by nT, where n is an integer greater than zero, and T is a delay interval. The method further includes multiplying the continuous-time digital signal and each of the delayed versions by one or more associated coefficients, so as to produce a set of products, then adding the set of products, so as to produce a sum value corresponding to the analog signal processed by a transfer function defined by the associated coefficients. The individual bit paths of the continuous-time digital signal are multiplied by the coefficients, and the resulting products are combined by a binary-weighted adder.
摘要翻译：一种连续时间数字处理模拟信号的方法包括经由不包括周期性采样的技术从模拟信号产生连续时间数字信号，然后产生连续时间数字信号的一个或多个延迟版本。每个延迟版本延迟nT，其中n是一个大于零的整数，T是一个延迟间隔。该方法进一步包括将连续时间数字信号和每个延迟版本乘以一个或多个相关系数，以便产生一组产品，然后添加该组产品，以便产生对应于模拟信号由相关系数定义的传递函数处理。连续时间数字信号的各个位路径被乘以系数，并且所得到的乘积由二进制加权加法器组合。

47. 发明申请

WO00044099A1 A LOW ENERGY ADC 审中-公开
标题翻译：低能量ADC
公开(公告)号：WO00044099A1
公开(公告)日：2000-07-27
申请号：PCT/SE2000/000053
申请日：2000-01-13
IPC分类号： H03M1/12 , H03M1/00 , H03M1/34
CPC分类号： H03M1/002 , H03M1/1215
摘要： The present invention relates to a parallel analog to digital converter (ADC) that includes at least two A/D channels which have an input and an output, where the analog input signal is converter to a digital output signal, and where each of the inputs of the A/D channels is coupled to a sample and hold unit, a multiplexing unit which includes at least two inputs, where each of the inputs is coupled to the output of the A/D channel, a time control unit for clocking the A/D channels and for controlling the multiplexing unit, wherein the analog to digital converter is provided with means for switching between a so-called idle mode and a so-called normal mode. The invention also relates to a method of saving energy in parallel analog to digital conversion.
摘要翻译：本发明涉及一种并行模数转换器（ADC），其包括具有输入和输出的至少两个A / D通道，其中模拟输入信号被转换为数字输出信号，并且其中每个输入的A / D信道耦合到采样和保持单元，复用单元，其包括至少两个输入，其中每个输入耦合到A / D通道的输出;时间控制单元，用于对A / D通道并用于控制多路复用单元，其中模数转换器具有用于在所谓的空闲模式和所谓的正常模式之间切换的装置。本发明还涉及一种在并行模数转换中节省能量的方法。

48. 发明申请

WO00041309A1 METHOD AND SYSTEM FOR QUANTIZING AN ANALOG SIGNAL UTILIZING A CLOCKED RESONANT TUNNELING DIODE PAIR 审中-公开
标题翻译：使用时钟谐振隧道二极管对模拟信号进行定量的方法和系统
公开(公告)号：WO00041309A1
公开(公告)日：2000-07-13
申请号：PCT/US2000/000171
申请日：2000-01-05
IPC分类号： H03M1/36 , H03K3/315 , H03M1/06 , H03M1/34
CPC分类号： B82Y10/00 , H03K3/315 , H03M1/0682 , H03M1/34
摘要： A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the input terminal. A second negative-resistance device has a first terminal coupled to the input terminal and a second terminal coupled to the inverted clock terminal. An output terminal coupled to the first negative-resistance device and the second negative-resistance device to provide a quantized output signal.
摘要翻译：用于量化模拟信号的系统包括用于接收模拟输入信号的输入端子，用于接收时钟信号的时钟端子和用于接收反相时钟信号的反相时钟端子。第一负电阻器件具有耦合到时钟端子的第一端子和耦合到输入端子的第二端子。第二负电阻器件具有耦合到输入端的第一端子和耦合到反相时钟端子的第二端子。输出端子，耦合到第一负电阻装置和第二负电阻装置，以提供量化的输出信号。

49. 发明申请

WO00011790A1 FLOATING-POINT ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：浮点数模数转换器
公开(公告)号：WO00011790A1
公开(公告)日：2000-03-02
申请号：PCT/SE1999/001406
申请日：1999-08-19
IPC分类号： G06F3/05 , H03M1/12 , H03M1/18 , H03M1/34
CPC分类号： H03M1/186
摘要： The demand on very high resolution A/D converter can be eliminated by using the invented floating-point A/D converter when the resolution is merely used for covering the signal dynamic range rather than the quantization accuracy. This can be achieved by producing m (>1) amplified analog signals with amplifivations 2 where k=constant and i=1, 2, ..., m. The largest linearly amplified signal will be selected by a logic circuit (after sampling) and converted into an n-bit digital data code by an A/D converter. In the same time, the logic circuit produces an m-bit logic flag code. The n-bit data code (u), the m-bit logic flag code (v) and the constant k are combined to form a final digital output uv with n+(m-1)k bits. In this way, the resolution and dynamic range can be designed independently. Unlike the known logarithmic amplifier solution, the floating-point A/D converter gives a linear digital code output ditectly without using any lookup table. For large and small signals, the effective resolutions are kept constant (or quasi-constant to be accurate). It is also very useful to work with a small input range imposed by a low power supply voltage since its virtual input range is much larger than the actual one. As an A/D converter, its accuracy distribution along the signal amplitude is more rational, an advantage similar to that of a floating-point number representation.
摘要翻译：当分辨率仅用于覆盖信号动态范围而不是量化精度时，通过使用本发明的浮点A / D转换器可以消除对非常高分辨率A / D转换器的需求。这可以通过产生具有放大2（i-1）k>其中k =常数和i = 1,2，...，m的m（> 1）个放大模拟信号来实现。最大的线性放大信号将由逻辑电路（采样后）选择，并由A / D转换器转换为n位数字数据。同时，逻辑电路产生一个m位逻辑标志码。 n比特数据码（u），m位逻辑标志码（v）和常数k被组合以形成具有n +（m-1）k比特的最终数字输出uv k。这样，分辨率和动态范围可以独立设计。与已知的对数放大器解决方案不同，浮点A / D转换器在不使用任何查找表的情况下给出线性数字代码输出。对于大信号和小信号，有效分辨率保持恒定（或准常数准确）。使用低电源电压施加的小输入范围也非常有用，因为它的虚拟输入范围比实际输入范围大得多。作为A / D转换器，其沿着信号幅度的精度分布更合理，具有与浮点数表示相似的优点。

50. 发明申请

WO99016173A1 ANALOG-DIGITAL CONVERTER WITH TREE-STRUCTURED FOLDING CIRCUIT 审中-公开
标题翻译：具有树状结构的折叠电路的模拟数字转换器
公开(公告)号：WO99016173A1
公开(公告)日：1999-04-01
申请号：PCT/FR1998/002013
申请日：1998-09-21
IPC分类号： H03M1/36 , H03M1/34
CPC分类号： H03M1/368
摘要： The invention concerns analog-digital converters, more precisely it concerns converters with signal folding which set up two so-called folded analog signals, whose variation curves depending on a voltage Vin to be converted intersect at multiple points. The patented architecture comprises: means (A0 to A10) for setting up n voltage pairs (VAk, V'Ak) varying with Vin and intersecting for values Vin = Vk evenly distributed; at least two current switching circuits (CA1 to CA4), each of which has at least three input pairs (E,Eb; F,Fb; G,Gb) and at least two outputs called direct output (B) and inverse output (C). The direct outputs, connected with each other, supply a folded signal SR; the inverse outputs supply a complementary folded signal SRb. Each switching circuit receives three pairs of voltages of rank k-1, k and k+1, and comprises a current source (SC) powering a group of branches mounted in tree structure. The distribution of current in each branch connection is a function of voltage pairs of rank k-1, k, k+1, and said circuit direct and inverse outputs are respectively taken on two different branches of the tree structure final stage.
摘要翻译：本发明涉及模拟数字转换器，更确切地说，它涉及具有信号折叠的转换器，其设置了两个所谓的折叠模拟信号，其变化曲线取决于要转换的电压Vin在多个点处相交。获得专利的架构包括：用于设置以Vin变化的n个电压对（VAk，V'Ak）的装置（A0至A10），对于均匀分布的值Vin = Vk相交; 至少两个电流开关电路（CA1至CA4），每个电流开关电路具有至少三个输入对（E，Eb; F，Fb; G，Gb）和至少两个称为直接输出（B）和反向输出（C ）。彼此连接的直接输出提供折叠信号SR; 反向输出提供互补折叠信号SRb。每个开关电路接收三对等级k-1，k和k + 1的电压，并且包括为安装在树结构中的一组分支供电的电流源（SC）。每个分支连接中的电流分布是等级k-1，k，k + 1的电压对的函数，所述电路直接和反向输出分别取决于树结构最后阶段的两个不同分支。

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