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1. 发明申请

WO2006014692A3 CMOS NEGATIVE RESISTANCE/Q ENHANCEMENT METHOD AND APPARATUS 审中-公开
标题翻译： CMOS负极电阻/ Q增强方法和设备
公开(公告)号：WO2006014692A3
公开(公告)日：2006-03-16
申请号：PCT/US2005025671
申请日：2005-07-20
申请人： UNIV COLUMBIA , STANIC NEBOJSA , TSIVIDIS YANNIS
发明人： STANIC NEBOJSA , TSIVIDIS YANNIS
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/124 , H03B2201/036
摘要： An apparatus for optimizing a quality factor Q associated with an electrical resonator system includes an LC resonator and an optimizing circuit for providing a negative resistance. The optimizing circuit is electrically coupled to the resonator circuit, and includes two CMOS transistor pairs with the gates of the PMOS transistors cross-coupled with inputs to the resonator through capacitors, and the gates of the NMOS transistor cross-coupled with the inputs to the resonator through capacitors. The optimizing circuit receives at least one control voltage for varying the negative resistance by selectively biasing the PMOS transistors and NMOS transistors. The optimizing circuit also includes a current source for providing a controlled current to the CMOS transistor pairs. The current source is situated either between a supply voltage and the CMOS transistor pairs, or between the CMOS transistor pairs and a ground reference voltage. A current-control voltage controls the current flowing through the CMOS transistor pairs.
摘要翻译：用于优化与电谐振器系统相关联的质量因数Q的装置包括LC谐振器和用于提供负电阻的优化电路。优化电路电耦合到谐振器电路，并且包括两个CMOS晶体管对，其中PMOS晶体管对的栅极通过电容器与谐振器的输入交叉耦合，并且NMOS晶体管的栅极与输入交叉耦合到谐振器通过电容器。优化电路通过选择性地偏置PMOS晶体管和NMOS晶体管来接收用于改变负电阻的至少一个控制电压。优化电路还包括用于向CMOS晶体管对提供受控电流的电流源。电流源位于电源电压和CMOS晶体管对之间，或位于CMOS晶体管对与接地参考电压之间。电流控制电压控制流过CMOS晶体管对的电流。

2. 发明申请

WO2005004373A3 CONTINUOUS-TIME DIGITAL SIGNAL GENERATION, TRANSMISSION, STORAGE AND PROCESSING 审中-公开
标题翻译：连续数字信号的产生，传输，存储和处理
公开(公告)号：WO2005004373A3
公开(公告)日：2005-12-29
申请号：PCT/US2004020814
申请日：2004-06-28
申请人： UNIV COLUMBIA , TSIVIDIS YANNIS
发明人： TSIVIDIS YANNIS
IPC分类号： G06F7/544 , H03H17/02 , H03M1/12 , H03M1/36 , H03M1/34
CPC分类号： G06F7/5443 , H03H17/0289 , H03M1/125 , H03M1/36
摘要： A method of digitally processing an analog signal in continuous time includes producing a continuous-time digital signal from an analog signal via a technique that does not include periodic sampling, then producing one or more delayed versions of the continuous-time digital signal. Each delayed version is delayed by nT, where n is an integer greater than zero, and T is a delay interval. The method further includes multiplying the continuous-time digital signal and each of the delayed versions by one or more associated coefficients, so as to produce a set of products, then adding the set of products, so as to produce a sum value corresponding to the analog signal processed by a transfer function defined by the associated coefficients. The individual bit paths of the continuous-time digital signal are multiplied by the coefficients, and the resulting products are combined by a binary-weighted adder.
摘要翻译：一种连续时间数字处理模拟信号的方法包括经由不包括周期性采样的技术从模拟信号产生连续时间数字信号，然后产生连续时间数字信号的一个或多个延迟版本。每个延迟版本延迟nT，其中n是一个大于零的整数，T是一个延迟间隔。该方法进一步包括将连续时间数字信号和每个延迟版本乘以一个或多个相关系数，以便产生一组产品，然后添加该组产品，以便产生对应于模拟信号由相关系数定义的传递函数处理。连续时间数字信号的各个位路径被乘以系数，并且所得到的乘积由二进制加权加法器组合。

3. 发明申请

WO02056558A9 ACTIVE FILTER CIRCUIT WITH DYNAMICALLY MODIFIABLE INTERNAL GAIN 审中-公开
公开(公告)号：WO02056558A9
公开(公告)日：2002-12-05
申请号：PCT/US0204668
申请日：2002-01-10
申请人： UNIV COLUMBIA , PALASKAS GEORGE , TSIVIDIS YANNIS , TOTH LASZLO
发明人： PALASKAS GEORGE , TSIVIDIS YANNIS , TOTH LASZLO
IPC分类号： H03B1/00 , H03F1/00 , H03G1/04 , H03G3/00 , H03G5/00 , H03G7/00 , H03H11/04 , H03H11/12 , H03K5/00 , H04L27/22
CPC分类号： H03G1/04 , H03G3/001 , H03G7/00 , H03H11/04 , H03H11/1252 , H03H11/1256 , H03H11/126 , H03H11/1291
摘要： Techniques are provided for the implementation of a signal processing circuit (100) which expands the dynamic range of the signal processing circuit (100) without interrupting the output of the circuit. The techniques can receive an input signal (104), proce ss the signal (104) through one of a plurality of dynamically modifiable signal processing circuits, and switch (130) to processing the signal through another of the plurality of signal processing circuits without disturbing the output of the system.

4. 发明申请

WO2006102313A3 SYSTEMS AND METHODS FOR COMPANDING ADC-DSP-DAC COMBINATIONS 审中-公开
标题翻译：用于组合ADC-DSP-DAC组合的系统和方法
公开(公告)号：WO2006102313A3
公开(公告)日：2007-03-15
申请号：PCT/US2006010204
申请日：2006-03-20
申请人： UNIV COLUMBIA , KLEIN ARI , TSIVIDIS YANNIS
发明人： KLEIN ARI , TSIVIDIS YANNIS
IPC分类号： G06F17/10
CPC分类号： H03M7/50 , H03M1/186
摘要： Systems and methods for resizing a signal for use with a fixed-point DSP are provided. More specifically, a process called companding is used in conjunction with fixed- point devices to resize a signal to make use of the available range of these devices. In some embodiments, companding is used to improve the signal-to-noise and distortion ratio. Also, information loss associated with quantization and rounding errors can be reduced in some embodiments.
摘要翻译：提供了用于调整用于定点DSP的信号大小的系统和方法。更具体地说，称为压扩的过程与定点设备结合使用以调整信号的大小以利用这些设备的可用范围。在一些实施例中，使用压扩来提高信噪比和失真比。此外，在一些实施例中，可以减少与量化和舍入误差相关联的信息丢失。

5. 发明申请

WO02056558A2 ACTIVE FILTER CIRCUIT WITH DYNAMICALLY MODIFIABLE INTERNAL GAIN 审中-公开
标题翻译：主动滤波电路具有动态可修改内部增益
公开(公告)号：WO02056558A2
公开(公告)日：2002-07-18
申请号：PCT/US0204668
申请日：2002-01-10
申请人： UNIV COLUMBIA , PALASKAS GEORGE , TSIVIDIS YANNIS , TOTH LASZLO
发明人： PALASKAS GEORGE , TSIVIDIS YANNIS , TOTH LASZLO
IPC分类号： H03B1/00 , H03F1/00 , H03G1/04 , H03G3/00 , H03G5/00 , H03G7/00 , H03H11/04 , H03H11/12 , H03K5/00 , H04L27/22
CPC分类号： H03G1/04 , H03G3/001 , H03G7/00 , H03H11/04 , H03H11/1252 , H03H11/1256 , H03H11/126 , H03H11/1291
摘要： Techniques are provided for the implementation of a signal processing circuit (100) which expands the dynamic range of the signal processing circuit (100) without interrupting the output of the circuit. The techniques can receive an input signal (104), proce ss the signal (104) through one of a plurality of dynamically modifiable signal processing circuits, and switch (130) to processing the signal through another of the plurality of signal processing circuits without disturbing the output of the system.
摘要翻译：提供技术用于实现信号处理电路（100），信号处理电路（100）扩展信号处理电路（100）的动态范围，而不中断电路的输出。这些技术可以接收输入信号（104），通过多个可动态修改的信号处理电路中的一个处理信号（104），以及开关（130），以通过多个信号处理电路中的另一个来处理该信号而不受干扰系统的输出。

6. 发明申请

WO2006039510A3 CONTINUOUS-TIME DIGITAL AMPLIFIER 审中-公开
标题翻译：连续数字放大器
公开(公告)号：WO2006039510A3
公开(公告)日：2006-08-10
申请号：PCT/US2005035223
申请日：2005-09-30
申请人： UNIV COLUMBIA , TSIVIDIS YANNIS
发明人： TSIVIDIS YANNIS
IPC分类号： H03F3/217 , H03F3/68
CPC分类号： H03F3/30 , H03F3/217 , H03F3/45475
摘要： A continuous-time digital amplifier (200, 300) includes a bit waveform generator (410) for producing one or more bit waveforms from a continuous-time digital signal (b). The amplifier also includes a fractional current source (202a-202c) for each of the one or more bit waveforms. Each fractional current source is controlled by the associated bit waveform. The output currents from the fractional current sources associated with the bit waveforms are combined to form a composite current that is used to drive a load. The amplifier may alternatively use fractional voltage sources instead of fractional current sources controlled by the bit waveforms, to generate a composite voltage to drive a load (308). The amplifier may also include a quantizer (410) for producing the continuous-time digital signal from an analog signal. The quantizer (410) produces the continuous-time digital signal without periodic sampling.
摘要翻译：连续时间数字放大器（200,300）包括用于从连续时间数字信号（b）产生一个或多个位波形的位波形发生器（410）。放大器还包括用于一个或多个位波形中的每一个的分数电流源（202a-202c）。每个分数电流源由关联的位波形控制。来自与位波形相关的分数电流源的输出电流被组合以形成用于驱动负载的复合电流。放大器可以替代地使用分数电压源而不是由位波形控制的分数电流源，以产生用于驱动负载（308）的复合电压。放大器还可以包括用于从模拟信号产生连续时间数字信号的量化器（410）。量化器（410）产生连续时间数字信号而不进行周期性采样。

7. 发明申请

WO2006034371A3 LOW VOLTAGE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER CIRCUITS 审中-公开
标题翻译：低电压工作电压放大器电路
公开(公告)号：WO2006034371A3
公开(公告)日：2006-10-12
申请号：PCT/US2005033885
申请日：2005-09-20
申请人： UNIV COLUMBIA , CHATTERJEE SHOURI , KINGET PETER R , TSIVIDIS YANNIS
发明人： CHATTERJEE SHOURI , KINGET PETER R , TSIVIDIS YANNIS
IPC分类号： H03F3/45
CPC分类号： H03K5/22 , H03F3/45071 , H03F2200/331
摘要： Circuits (Fig. 1) that operate with power supplies (VDD) of less than 1 Volt are present. More particularly, circuits (Fig. 1) that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (M1A, M1B) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor (MOS) to bipolar junction transistors may implement the techniques presented herein.
摘要翻译：存在电源（VDD）小于1伏特的电路（图1）。更具体地，示出了在这些电路中接近或低于晶体管（M1A，M1B）的阈值电压的电源电压（VDD））下工作的电路（图1）。提出了诸如运算跨导放大器，偏置电路，积分器，连续时间Σ-Δ调制器，跟踪和保持电路等各种电路和实施例。技术和电路可用于广泛的应用，并且从金属氧化物半导体（MOS）到双极结型晶体管的各种晶体管可以实现本文提出的技术。

8. 发明申请

WO2006039510A9 CONTINUOUS-TIME DIGITAL AMPLIFIER 审中-公开
标题翻译：连续数字放大器
公开(公告)号：WO2006039510A9
公开(公告)日：2006-05-11
申请号：PCT/US2005035223
申请日：2005-09-30
申请人： UNIV COLUMBIA , TSIVIDIS YANNIS
发明人： TSIVIDIS YANNIS
IPC分类号： H03F3/28
CPC分类号： H03F3/30 , H03F3/217 , H03F3/45475
摘要： A continuous-time digital amplifier includes a bit waveform generator for producing one or more bit waveforms from a continuous-time digital signal. The amplifier also includes a fractional current source for each of the one or more bit waveforms. Each fractional current source is controlled by the associated bit waveform. The output currents from the fractional current sources associated with the bit waveforms are combined to form a composite current that is used to drive a load. The amplifier may alternatively use fractional voltage sources instead of fractional current sources controlled by the bit waveforms, to generate a composite voltage to drive a load. The amplifier may also include a quantizer for producing the continuous-time digital signal from an analog signal. The quantizer produces the continuous-time digital signal without periodic sampling.
摘要翻译：连续时间数字放大器包括用于从连续时间数字信号产生一个或多个位波形的位波形发生器。放大器还包括用于一个或多个位波形中的每一个的分数电流源。每个分数电流源由相关的位波形控制。来自与比特波形关联的分数电流源的输出电流被组合以形成用于驱动负载的合成电流。可选地，放大器可以使用分数电压源代替由比特波形控制的分数电流源来产生合成电压以驱动负载。放大器还可以包括用于从模拟信号产生连续时间数字信号的量化器。量化器产生连续时间数字信号而无需定期采样。

9. 发明申请

WO2012173937A3 CELL MODELING 审中-公开
标题翻译：细胞建模
公开(公告)号：WO2012173937A3
公开(公告)日：2013-05-02
申请号：PCT/US2012041948
申请日：2012-06-11
申请人： SENDYNE CORP , TSIVIDIS YANNIS
发明人： TSIVIDIS YANNIS
IPC分类号： G01R31/36 , G01R19/165
CPC分类号： G06F17/5036 , G01R31/2848 , G01R31/3651
摘要： An arrangement provides simulation of important battery factors such as state of charge or state of health, and the estimates are provided to the human user in ways that permit the human user to make better use of the battery, for example in an electric car. The arrangement uses modeling elements that communicate with each other by means of an analog bus. Some lines on the analog bus are voltages that are intended to be inputs to the simulation or actual measured values from a physical system. Other lines, importantly, are "voltages" that are intended to communicate characteristics of interest such as open-circuit voltage of a cell. Still other lines may be "voltages" that merely pass messages between modeling elements, the voltages not necessarily representing any real-life measurable such as the afore-mentioned temperature value.
摘要翻译：一种安排提供了诸如充电状态或健康状态等重要电池因素的模拟，并且以允许人类用户更好地利用电池（例如电动汽车）的方式向人类用户提供估计。该装置使用通过模拟总线相互通信的建模元件。模拟总线上的一些线路是用于从物理系统输入到仿真或实际测量值的电压。其他线路重要的是旨在传达感兴趣特性的“电压”，例如电池的开路电压。其他线路可以是仅在建模元件之间传递消息的“电压”，电压不一定代表任何现实生活中可测量的，例如上述温度值。

10. 发明申请

WO2004079782A3 POWER DISSIPATION REDUCTION IN WIRELESS TRANSCEIVERS 审中-公开
标题翻译：无线收发器中的电力消耗减少
公开(公告)号：WO2004079782A3
公开(公告)日：2005-07-28
申请号：PCT/US2004005838
申请日：2004-02-27
申请人： THETA MICROELECTRONICS INC , TSIVIDIS YANNIS
发明人： TSIVIDIS YANNIS
IPC分类号： H04B1/10 , H04B1/16 , H04B1/00
CPC分类号： H04B1/109
摘要： Methods and circuits for reducing power dissipation in wireless transceivers and other electronic circuits and systems. Embodiments of the present invention use bias current reduction, impedance scaling, and gain changes either separately or in combination to reduce power dissipation. For example, bias currents are reduced in response to a need for reduced signal handling capability, impedances are scaled thus reducing required drive and other bias currents in response to a strong received signal, or gain is increased and impedances are scaled in response to a low received signal in the presence of no or weak interfering signals.
摘要翻译：用于减少无线收发器和其他电子电路和系统功耗的方法和电路。本发明的实施例分别使用偏置电流减小，阻抗缩放和增益变化来组合以减少功耗。例如，响应于需要降低的信号处理能力而减小偏置电流，阻抗被缩放，从而响应于强接收信号而减少所需的驱动和其它偏置电流，或者增益增加，并且阻抗被响应于低电平在没有或弱的干扰信号的情况下接收信号。

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