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41. 发明申请

WO2009035586A1 CONFIGURATION CONTEXT SWITCHER 审中-公开
标题翻译：配置语境切换器
公开(公告)号：WO2009035586A1
公开(公告)日：2009-03-19
申请号：PCT/US2008/010526
申请日：2008-09-08
申请人： TABULA, INC. , CHANDLER, Trevis , REDGRAVE, Jason , ENTINGER, Joe , VOOGEL, Martin , TEIG, Steven
发明人： CHANDLER, Trevis , REDGRAVE, Jason , ENTINGER, Joe , VOOGEL, Martin , TEIG, Steven
IPC分类号： G11C7/00
CPC分类号： H03K19/0008 , G06F15/7867 , G11C7/1045 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H03K3/0372 , H03K19/17732 , H03K19/17748 , H03K19/17752 , H03K19/17768 , H01L2924/00 , H01L2924/00014
摘要： Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
摘要翻译：一些实施例向IC提供配置上下文切换器。 IC包括几个可配置电路，每个可配置电路可以在任何给定时间根据当时接收到的配置数据集配置执行多个操作之一。 IC包括多个存储电路，用于存储每个可配置电路的几个配置数据组。 IC还包括用于将可配置电路可切换地连接到不同组的存储电路以接收不同组的配置数据集的上下文切换互连电路。上下文切换器包括用于重新定时来自配置存储元件的数据的一个或多个阶段。这些阶段可以包括互连电路或存储电路。一些实施例构建配置数据存储元件中的一个阶段。一些实施例对配置数据位进行编码，并因此利用上下文切换器中的解码器对编码的配置数据进行解码。

42. 发明申请

WO2008118561A1 METHOD AND DEVICE FOR PROGRAMMING ANTI-FUSES 审中-公开
标题翻译：用于编制抗熔体的方法和装置
公开(公告)号：WO2008118561A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/054240
申请日：2008-02-19
申请人： FREESCALE SEMICONDUCTOR INC. , PERKINS, Geoffrey W.
发明人： PERKINS, Geoffrey W.
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , G11C17/16 , G11C17/18 , H03K19/17748 , H03K19/17764 , H03K19/17768 , H03K19/1778
摘要： A device includes an anti-fuse (122) including a first electrode that can be selectively coupled to a first voltage reference (121) and a second electrode that can be selectively coupled to a second voltage reference (123). The device further includes a shunt transistor (124) including a first current electrode coupled to the first electrode of the anti-fuse (122), a second current electrode coupled to the second electrode of the anti-fuse (122), and a control electrode. The device additionally includes control logic (126) configured to disable the shunt transistor in response to a first program operation intended for the anti-fuse. The control logic (126) also is configured to enable the shunt transistor in response to a second program operation not intended for the anti-fuse.
摘要翻译：一种装置包括抗熔丝（122），其包括能够选择性地耦合到第一电压参考（121）的第一电极和可选择性地耦合到第二电压参考（123）的第二电极。该装置还包括分流晶体管（124），其包括耦合到反熔丝（122）的第一电极的第一电流电极，耦合到反熔丝（122）的第二电极的第二电流电极，以及控制电极。该装置还包括被配置为响应于用于反熔丝的第一编程操作来禁用分流晶体管的控制逻辑（126）。控制逻辑（126）还被配置为响应于不针对反熔丝的第二编程操作使能分流晶体管。

43. 发明申请

WO2005081799A3 UPGRADEABLE AND RECONFIGURABLE PROGRAMMABLE LOGIC DEVICE 审中-公开
标题翻译：可升级和可重新编写的可编程逻辑器件
公开(公告)号：WO2005081799A3
公开(公告)日：2006-01-26
申请号：PCT/US2005004031
申请日：2005-02-10
申请人： LATTICE SEMICONDUCTOR CORP
发明人： AGRAWAL OM , TANG HOWARD , WONG JACK
IPC分类号： H03K19/177
CPC分类号： H03K19/17772 , H03K19/17732 , H03K19/1776 , H03K19/17768
摘要： Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.
摘要翻译：公开了用于编程和/或重新配置这些设备的可编程逻辑器件和技术。例如，根据本发明的一个实施例，公开了一种可编程逻辑器件，其包括闪速存储器和SRAM，并且包括用于对闪速存储器和/或SRAM进行编程的多个数据端口。

44. 发明申请

WO02011289A1 SECURE PROGRAMMABLE LOGIC DEVICE 审中-公开
标题翻译：安全可编程逻辑器件
公开(公告)号：WO02011289A1
公开(公告)日：2002-02-07
申请号：PCT/US2001/040935
申请日：2001-06-11
IPC分类号： G06F21/22 , G06F12/14 , G06F21/00 , H03K19/173 , H03K19/177 , H04L9/10 , G11C16/22
CPC分类号： G06F21/76 , G06F12/1433 , G06F21/606 , G06F21/74 , G06F21/79 , G06F2221/2105 , G06F2221/2143 , H03K19/17704 , H03K19/17768
摘要： A programmable logic chip (21) and configuration memory chip (23) are mounted within a multi-chip module (25) to form a single package. The configuration memory has a security bit (24) which in a first state allows programming a read-back of configuration data in the memory chip via external pins (29) of the package, and in a second state allows only erase command to be communicated to the memory chip via the external pins. The internal data transfer connection (27) between the memory chip and programmable logic chip is enabled when the security bit is in the second state and the memory chip is in a read-back mode, allowing configuration data to be loaded into the logic chip upon power up.
摘要翻译：可编程逻辑芯片（21）和配置存储器芯片（23）安装在多芯片模块（25）内以形成单个封装。配置存储器具有安全位（24），其处于第一状态允许通过封装的外部引脚（29）对存储器芯片中的配置数据进行读回编程，并且在第二状态仅允许擦除命令被传送通过外部引脚到存储器芯片。当安全位处于第二状态并且存储器芯片处于回读模式时，存储器芯片和可编程逻辑芯片之间的内部数据传输连接（27）被使能，允许将配置数据加载到逻辑芯片中充电。

45. 发明申请

WO1998023033A1 LOOKUP TABLES WHICH DOUBLE AS SHIFT REGISTERS 审中-公开
标题翻译：作为移动寄存器的LOOKUP表
公开(公告)号：WO1998023033A1
公开(公告)日：1998-05-28
申请号：PCT/US1997009314
申请日：1997-06-16
申请人： XILINX, INC.
发明人： XILINX, INC. , BAUER, Trevor, J.
IPC分类号： H03K19/173
CPC分类号： G11C19/00 , H03K19/1736 , H03K19/17728 , H03K19/17736 , H03K19/17768
摘要： A logic element for an FPGA which can be configured as any one of a random access memory, a shift register and a lookup table. The logic element includes a plurality of memory cells (790l...7904) which are interconnected such that the data output of each cell (790i) can serve as the input to the next memory cell (790i+l). Thus the logic element effectively functions as a shift register. Shift registers of arbitrary length can be created by using a lookup table address multiplexer (200) to select any memory cell (790i) output (not necessarily the last memory cell (790i) output) of the lookup table, and by chaining lookup tables of plural logic elements in series.
摘要翻译：用于FPGA的逻辑元件，其可以被配置为随机存取存储器，移位寄存器和查找表中的任何一个。逻辑元件包括互连的多个存储器单元（790 1 ... 7904），使得每个单元（790i）的数据输出可以用作下一个存储器单元（790i + 1）的输入。因此，逻辑元件有效地用作移位寄存器。可以通过使用查找表地址多路复用器（200）来选择查找表的任何存储单元（790i）输出（不一定是最后一个存储单元（790i）输出）并通过链接查找表的查找表来创建任意长度的移位寄存器多个逻辑元素串联。

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