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41. 发明申请

WO2007031930A2 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH DIFFERENT METALLIC GATES 审中-公开
标题翻译：制造具有不同金属门的半导体装置的方法
公开(公告)号：WO2007031930A2
公开(公告)日：2007-03-22
申请号：PCT/IB2006/053205
申请日：2006-09-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LANDER, Robert, J., P. , VAN DAL, Mark , HOOKER, Jacob C.
发明人： LANDER, Robert, J., P. , VAN DAL, Mark , HOOKER, Jacob C.
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28097 , H01L29/4958 , H01L29/66545 , H01L29/78
摘要： A method is described for forming gate structures with different metals on a single substrate. A thin semiconductor layer (26) is formed over gate dielectric (24) and patterned to be present in a first region (16) not a second region (18). Then, metal (30) is deposited and patterned to be present in the second region not the first. Then, a fully suicided gate process is carried out to result in a fully suicided gate structure in the first region and a gate structure in the second region including the fully suicided gate structure above the deposited metal (30).
摘要翻译：描述了用于在单个衬底上形成具有不同金属的栅极结构的方法。在栅极电介质（24）上方形成薄半导体层（26）并将其图案化以存在于不是第二区域（18）的第一区域（16）中。然后，沉积并图案化金属（30）以存在于不是第一区域的第二区域中。然后，执行完全硅化的栅极工艺以在第一区域中产生完全硅化的栅极结构，并在第二区域中产生包括在沉积的金属（30）上方的全硅化栅极结构的栅极结构。

42. 发明申请

WO2006137371A1 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：WO2006137371A1
公开(公告)日：2006-12-28
申请号：PCT/JP2006/312273
申请日：2006-06-20
申请人：日本電気株式会社 , 辰巳徹 , 寺井真之 , 長谷卓 , 高橋健介
发明人：辰巳徹 , 寺井真之 , 長谷卓 , 高橋健介
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/41 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L29/42372 , H01L29/4975 , H01L29/66545
摘要：　半導体基板上に、Ｐチャネル形成領域上に形成されたゲート絶縁膜及びゲート電極、並びにゲート側壁部を持つ第１の電界効果型トランジスタ領域と、Ｎチャネル形成領域上に形成されたゲート絶縁膜及びゲート電極、並びにゲート側壁部を持つ第２の電界効果型トランジスタ領域とを有する半導体装置において、第１及び第２の電界効果トランジスタ領域は、前記ゲート電極が、Ｍ（ｘ）Ｓｉ（１－ｘ）（０＜ｘ＜１）で表される金属Ｍのシリサイドを主成分とし、かつ前記ゲート電極の高さをｔ１、ゲート側壁部の高さをｔ２、ゲート長をＬとしたとき、ｔ１－ｔ２＜Ｌ／２を満たし、さらにＰチャネル形成領域上のゲート電極の高さがＮチャネル形成領域上のゲート電極の高さよりも高いことを特徴とする半導体装置。
摘要翻译：在半导体器件中，半导体衬底设置有形成在P沟道形成区域上的具有栅极绝缘膜，栅电极和栅极侧壁部的第一场效应晶体管区域; 以及形成在N沟道形成区域上的具有栅极绝缘膜，栅电极和栅极侧壁部的第二场效应晶体管区域。半导体器件的特征在于，第一和第二场效应晶体管区域中的栅电极具有表示为M（x）Si（1-x）（0

43. 发明申请

WO2006103158A2 INTEGRATION SCHEME FOR FULLY SILICIDED GATE 审中-公开
标题翻译：完整硅胶整合方案
公开(公告)号：WO2006103158A2
公开(公告)日：2006-10-05
申请号：PCT/EP2006/060632
申请日：2006-03-10
申请人： INFINEON TECHNOLOGIES AG , CULMSEE, Marcus , DONI, Lothar , WENDT, Hermann
发明人： CULMSEE, Marcus , DONI, Lothar , WENDT, Hermann
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/665 , H01L21/28097 , H01L29/66545 , H01L29/6656
摘要： To form a semiconductor device, a silicon (e.g., polysilicon) gate layer is formed over a gate dielectric and a sacrificial layer (preferably titanium nitride) is formed over the silicon gate layer. The silicon gate layer and the sacrificial layer are patterned to form a gate structure. A spacer, such, as an oxide sidewall spacer and a nitride sidewall spacer, is formed adjacent the sidewall of the gate structure. The semiconductor body is then doped to form a source region and a drain region that are self-aligned to the spacers. The sacrificial layer can then be removed selectively with respect to the oxide sidewall spacer, the nitride sidewall spacer and the silicon gate. A metal layer (e.g., nickel) is formed over the source region, the drain region and the silicon gate and reacted with these regions to form a suicided source contact, a suicided drain contact and a suicided gate.
摘要翻译：为了形成半导体器件，在栅极电介质上形成硅（例如多晶硅）栅极层，并且在硅栅极层上形成牺牲层（优选氮化钛）。图案化硅栅极层和牺牲层以形成栅极结构。在栅极结构的侧壁附近形成间隔物，例如氧化物侧壁间隔物和氮化物侧壁间隔物。然后，半导体体被掺杂以形成与间隔物自对准的源极区域和漏极区域。然后可以相对于氧化物侧壁间隔物，氮化物侧壁间隔物和硅栅极选择性地去除牺牲层。在源极区域，漏极区域和硅栅极上形成金属层（例如镍），并且与这些区域反应以形成硅化源极接触，硅化的漏极接触和硅化的栅极。

44. 发明申请

WO2005096366A1 A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A SILICIDED GATE ELECTRODE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT INCLUDING THE SAME 审中-公开
标题翻译：制造具有硅化物电极的半导体器件的方法和用于制造包括其的集成电路的方法
公开(公告)号：WO2005096366A1
公开(公告)日：2005-10-13
申请号：PCT/US2005/010288
申请日：2005-03-28
申请人： TEXAS INSTRUMENTS INCORPORATED , LU, Jiong-Ping , BU, Haowen , YU, Shaofeng , JIANG, Ping
发明人： LU, Jiong-Ping , BU, Haowen , YU, Shaofeng , JIANG, Ping
IPC分类号： H01L21/44
CPC分类号： H01L29/66507 , H01L21/28097 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilicon gate electrode over a substrate (110) and forming source/drain regions (170) in the substrate (110) proximate the polysilicon gate electrode. The method further includes forming a blocking layer (180) over the source/drain regions (170), the blocking layer (180) comprising . a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode (150).
摘要翻译：本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。除了其他可能的步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成多晶硅栅电极，并在靠近多晶硅栅电极的衬底（110）中形成源/漏区（170）。该方法还包括在源极/漏极区域（170）上形成阻挡层（180），阻挡层（180）包括。金属硅化物，并且硅化所述多晶硅栅电极以形成硅化物栅电极（150）。

45. 发明申请

WO2005083780A2 CMOS SILICIDE METAL GATE INTEGRATION 审中-公开
标题翻译： CMOS硅化金属栅集成
公开(公告)号：WO2005083780A2
公开(公告)日：2005-09-09
申请号：PCT/US2005005565
申请日：2005-02-22
申请人： IBM , AMOS RICKY S , BOYD DIANE C , CABRAL CYRIL JR , KAPLAN RICHARD D , KEDZIERSKI JAKUB T , KU VICTOR , LEE WOO-HYEONG , LI YING , MOCUTA ANDA C , NARAYANAN VIJAY , STEEGEN AN L , SURENDRA MAHESWAREN
发明人： AMOS RICKY S , BOYD DIANE C , CABRAL CYRIL JR , KAPLAN RICHARD D , KEDZIERSKI JAKUB T , KU VICTOR , LEE WOO-HYEONG , LI YING , MOCUTA ANDA C , NARAYANAN VIJAY , STEEGEN AN L , SURENDRA MAHESWAREN
IPC分类号： H01L21/28 , H01L21/336 , H01L21/339 , H01L21/60 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了互补金属氧化物半导体集成工艺，由此在栅极电介质顶上制造多个硅化金属栅极。不管硅化物金属栅极的尺寸如何，使用本发明的集成方案形成的每个硅化金属栅极具有相同的硅化物金属相和基本相同的高度。本发明还提供了形成具有硅化触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

46. 发明申请

WO2005067034A1 A CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT 审中-公开
标题翻译：具有金属和硅化物电极的CMOS器件及其制造方法
公开(公告)号：WO2005067034A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/043656
申请日：2004-12-22
申请人： INTEL CORPORATION , BRASK, Justin, K. , DOCZY, Mark, L. , KAVALIEROS, Jack , METZ, Matthew, V. , BARNS, Chris, E. , SHAH, Uday , DATTA, Suman , THOMAS, Christopher, D. , CHAU, Robert, S.
发明人： BRASK, Justin, K. , DOCZY, Mark, L. , KAVALIEROS, Jack , METZ, Matthew, V. , BARNS, Chris, E. , SHAH, Uday , DATTA, Suman , THOMAS, Christopher, D. , CHAU, Robert, S.
IPC分类号： H01L21/8238
CPC分类号： H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L27/1203 , H01L29/4975 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
摘要翻译：描述半导体器件及其形成方法。半导体器件包括形成在衬底的第一部分上的金属NMOS栅电极和形成在衬底的第二部分上的硅化物PMOS栅电极。

47. 发明申请

WO2004057659A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2004057659A1
公开(公告)日：2004-07-08
申请号：PCT/IB2003/006009
申请日：2003-12-15
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , VENEZIA, Vincent, C. , DACHS, Charles, J., J. , HOOKER, Jacob, C. , VAN DAL, Marcus, J., H.
发明人： VENEZIA, Vincent, C. , DACHS, Charles, J., J. , HOOKER, Jacob, C. , VAN DAL, Marcus, J., H.
IPC分类号： H01L21/28
CPC分类号： H01L29/41783 , H01L21/26586 , H01L21/28097 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/1045 , H01L29/4975 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833 , Y10T307/74
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided, at a surface thereof, with a source region (2) and a drain region (3) and with a gate region (4) between the source region (2) and the drain region (3), which gate region comprises a semiconductor region (4A) of a further semiconductor material that is separated from the surface of the semiconductor body (1) by a gate dielectric (5), and with spacers (6) adjacent to the gate region (4), for forming the source and drain regions (2,3), in which method the source region (2) and the drain region (3) are provided with a metal layer (7) which is used to form a compound (8) of the metal and the semiconductor material, and the gate region (4) is provided with a metal layer (7) which is used to form a compound (8) of the metal and the further semiconductor material. The known method in which different metal layers are used to silicidate source and drain regions and gate regions (2,3,4) has several drawbacks. A method according to the invention is characterized in that before the spacers (6) are formed, a sacrificial region (4B) of a material that may be selectively etched with respect to the semiconductor region (4A) is deposited on top of the semiconductor region (4A), and after the spacers (6) have been formed, the sacrificial layer (4B) is removed by etching, and after removal of the sacrificial layer (4B), a single metal layer (7) is deposited contacting the source, drain and gate regions (2,3,4). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate (4).
摘要翻译：本发明涉及一种制造具有场效应晶体管的半导体器件（10）的方法，该场效应晶体管在其表面上提供半导体材料的半导体本体（1），源极区（2）和漏极区域（3）和源极区域（2）和漏极区域（3）之间的栅极区域（4），该栅极区域包括从其表面分离的另一半导体材料的半导体区域（4A）半导体本体（1）通过栅极电介质（5）和与栅极区域（4）相邻的间隔物（6）形成源极和漏极区域（2,3），其中源区域（2））和漏区（3）设置有用于形成金属和半导体材料的化合物（8）的金属层（7），并且栅极区域（4）设置有金属层（7）），其用于形成金属的化合物（8）和另外的半导体材料。使用不同的金属层来硅化源极和漏极区域和栅极区域（2,3,4）的已知方法具有若干缺点。根据本发明的方法的特征在于，在形成间隔物（6）之前，可以相对于半导体区域（4A）选择性地蚀刻的材料的牺牲区域（4B）沉积在半导体区域（4A），并且在形成间隔物（6）之后，通过蚀刻去除牺牲层（4B），并且在去除牺牲层（4B）之后，沉积与源极接触的单个金属层（7）漏极和栅极区域（2,3,4）。这种方法一方面非常简单，因为它只需要单一的金属层和少量的直接步骤，并且它与现有的（硅）技术相兼容，另一方面它产生一个（MOS）FET 不会在完全硅化的栅极（4）中遭受耗尽层效应。

48. 发明申请

WO2004038778A1 GATE MATERIAL FOR SEMICONDUCTOR DEVICE FABRICATION 审中-公开
标题翻译：用于半导体器件制造的栅极材料
公开(公告)号：WO2004038778A1
公开(公告)日：2004-05-06
申请号：PCT/US2003/033561
申请日：2003-10-22
申请人： AMBERWAVE SYSTEMS CORPORATION
发明人： LOCHTEFELD, Anthony, J. , ANTONIADIS, Dimitri , CURRIE, Matthew, T.
IPC分类号： H01L21/28
CPC分类号： H01L29/7842 , H01L21/28079 , H01L21/28097 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66583 , H01L29/78654 , Y10S438/938
摘要： In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by the gate annealing step.
摘要翻译：在形成电子器件时，半导体层是预掺杂的，并且在栅极定义之前执行掺杂剂分布退火。或者，栅极由金属形成。因此，随后形成的浅源和漏极不受栅极退火步骤的影响。

49. 发明申请

WO0247146A3 DAMASCENE NiSi METAL GATE HIGH-K TRANSISTOR 审中-公开
标题翻译： DAMASCENE镍硅金属栅高K晶体管
公开(公告)号：WO0247146A3
公开(公告)日：2002-08-22
申请号：PCT/US0146551
申请日：2001-12-03
申请人： ADVANCED MICRO DEVICES INC
发明人： XIANG QI , BESSER PAUL R , BUYNOSKY MATTHEW S , FOSTER JOHN CLAYTON , KING PAUL L , PATON ERIC N
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/423
CPC分类号： H01L21/28185 , H01L21/28097 , H01L21/28194 , H01L29/495 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method for implementing a self-aligned low silicide gate (36) is archived by confining a low temperature silicidation metal (32) within a recess (28) overlying a channel and annealing to cause the low temperature silicidation metal (32) and its overlying silicon (34) to interact to form the self-aligned low temperature metal silicide gate (36). A planarization step is performed to remove the remaining unreacted silicon (34) by chemical mechanical polishing until no silicon (34) is detected. In order embodiments, the silicon (132) is deposited in the recess (28), followed by deposition of the silicidation metal (132) and annealing to form the metal silicide gate (136).
摘要翻译：一种用于实现自对准低硅化物栅极（36）的方法通过将低温硅化金属（32）限制在覆盖沟道的凹槽（28）内并退火以使低温硅化金属（32）及其上覆层硅（34）相互作用以形成自对准低温金属硅化物栅极（36）。执行平坦化步骤以通过化学机械抛光去除剩余的未反应的硅（34），直到没有检测到硅（34）。在顺序实施例中，硅（132）沉积在凹槽（28）中，随后沉积硅化金属（132）并退火以形成金属硅化物栅极（136）。

50. 发明申请

WO1994014198A1 A MOS TRANSISTOR HAVING A COMPOSITE GATE ELECTRODE AND METHOD OF FABRICATION 审中-公开
标题翻译：具有复合栅极电极的MOS晶体管及其制造方法
公开(公告)号：WO1994014198A1
公开(公告)日：1994-06-23
申请号：PCT/US1993011116
申请日：1993-11-16
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , CHAU, Robert, S. , FRASER, David, B. , CADIEN, Kenneth, C. , RAGHAVAN, Gopal , YAU, Leopoldo, D.
IPC分类号： H01L29/76
CPC分类号： H01L29/6659 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/665 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A novel, reliable, high performance MOS transistor (300) with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer (302) formed on a highly conductive layer (304). The composite gate electrode is formed on a gate insulating layer (301) which is formed on a silicon substrate (308). A pair of source/drain regions (310a, 310b) are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.
摘要翻译：一种具有与标准CMOS制造工艺兼容的复合栅电极的新颖可靠的高性能MOS晶体管（300）。复合栅电极包括形成在高导电层（304）上的多晶硅层（302）。复合栅电极形成在形成在硅衬底（308）上的栅极绝缘层（301）上。一对源极/漏极区（310a，310b）形成在衬底中并且与复合栅电极的外边缘自对准。

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