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31. 发明申请

WO2018101956A1 SELF-ALIGNED ELECTRODE NANO-CONTACTS FOR NON-VOLATILE RANDOM ACCESS MEMORY (RAM) BIT CELLS 审中-公开
公开(公告)号：WO2018101956A1
公开(公告)日：2018-06-07
申请号：PCT/US2016/064644
申请日：2016-12-02
申请人： INTEL CORPORATION
发明人： ATANASOV, Sarah E. , SURI, Satyarth , DOYLE, Brian S. , O'BRIEN, Kevin P. , OGUZ, Kaan , DOCZY, Mark L. , KUO, Charles C.
IPC分类号： H01L45/00 , H01L43/02
CPC分类号： H01L45/04 , H01L27/222 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L43/12 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： Self-aligned electrode nano-contacts for non-volatile random access memory (RAM) bit cells, and methods of fabricating electrode nano-contacts for non-volatile random access memory (RAM) bit cells, are described. In an example, semiconductor structure includes a conductive electrode disposed above a substrate. A non-volatile random access memory (RAM) element is disposed above the conductive electrode. The non-volatile RAM element has an uppermost surface with a surface area. A conductive contact is disposed on and is electrically connected to the uppermost surface of the non-volatile RAM element. The conductive contact has a surface area less than the surface area of the uppermost surface of the non-volatile RAM element at an interface of the conductive contact and the uppermost surface of the non-volatile RAM element.

32. 发明申请

WO2017171716A1 INTERCONNECT CAPPING PROCESS FOR INTEGRATION OF MRAM DEVICES AND THE RESULTING STRUCTURES 审中-公开
标题翻译： MRAM器件集成与互连结构的互连CAPPING过程
公开(公告)号：WO2017171716A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/024555
申请日：2016-03-28
申请人： INTEL CORPORATION
发明人： WIEGAND, Christopher J. , GOLONZKA, Oleg , RAHMAN, MD Tofizur , DOYLE, Brian S. , DOCZY, Mark L. , O'BRIEN, Kevin P. , OGUZ, Kaan , GHANI, Tahir , SURI, Satyarth
IPC分类号： H01L43/02 , H01L43/10 , H01L43/12
摘要： Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.
摘要翻译：描述了用于集成磁性随机存取存储器（MRAM）器件的互连包覆工艺以及所得到的结构的方法。在一个示例中，存储器结构包括设置在衬底上方的介电层的沟槽中的互连件，互连件包括设置在沟槽的底部并沿着沟槽的侧壁到介电层的最上表面的扩散阻挡层，设置在扩散阻挡层上并且凹陷在介电层的最上表面和扩散阻挡层的最上表面下方的导电填充层以及布置在导电填充层上和扩散阻挡层的侧壁部分之间的导电盖层。存储元件设置在互连的导电盖层上。

33. 发明申请

WO2017052631A1 PSTTM DEVICE WITH MULTI-LAYERED FILTER STACK 审中-公开
标题翻译：具有多层过滤器堆叠的PSTTM设备
公开(公告)号：WO2017052631A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052383
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： OGUZ, Kaan , O'BRIEN, Kevin P. , WIEGAND, Christopher J. , RAHMAN, MD Tofizur , DOYLE, Brian S. , DOCZY, Mark L. , GOLONZKA, Oleg , GHANI, Tahir , BROCKMAN, Justin S.
IPC分类号： H01L43/02 , H01L43/10 , H01L43/12
CPC分类号： H01L43/12 , H01F10/3272 , H01F10/3286 , H01F41/307 , H01L43/08 , H01L43/10
摘要： MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.
摘要翻译： MTJ材料堆栈，采用这种堆栈的pSTTM设备，以及采用这种pSTTM设备的计算平台。在一些实施例中，垂直MTJ材料堆叠包括设置在固定磁性层和反铁磁层或合成反铁磁（SAF）堆叠之间的多层过滤器堆叠。在一些实施例中，过滤器堆叠的非磁性层包括Ta，Mo，Nb，W或Hf中的至少一种。这些过渡金属可以是纯的形式或与其它成分合金化。

34. 发明申请

WO2016204750A1 RANDOM NUMBER GENERATOR 审中-公开
标题翻译：随机数发电机
公开(公告)号：WO2016204750A1
公开(公告)日：2016-12-22
申请号：PCT/US2015/036266
申请日：2015-06-17
申请人： INTEL CORPORATION
发明人： KUO, Charles C. , BROCKMAN, Justin S. , ALZATE VINASCO, Juan G. , OGUZ, Kaan , O'BRIEN, Kevin P. , DOYLE, Brian S. , DOCZY, Mark L. , SURI, Satyarth , CHAU, Robert S. , MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V.
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H01L43/02 , H01L43/08
摘要： Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.
摘要翻译：描述了一种装置，其包括：磁隧道结（MTJ）装置，其具有用于其自由和固定磁性层的平面外磁化，并且被配置为具有远离中心的磁化偏移并且更接近MTJ的切换阈值设备; 以及根据MTJ设备的电阻状态产生随机数的逻辑。

35. 发明申请

WO2014051996A1 VERTICAL MEANDER INDUCTOR FOR SMALL CORE VOLTAGE REGULATORS 审中-公开
标题翻译：用于小型电压稳压器的垂直式电感电感器
公开(公告)号：WO2014051996A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/059045
申请日：2013-09-10
申请人： INTEL CORPORATION
发明人： JEZEWSKI, Christopher J. , O'BRIEN, Kevin P.
IPC分类号： H01L27/00
CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
摘要翻译：描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。例如，半导体管芯包括衬底。集成电路设置在基板的有源表面上。电感器耦合到集成电路。电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。绝缘层具有起伏的形貌。

36. 发明申请

WO2018125204A1 PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (PSTTM) DEVICES WITH ENHANCED STABILITY AND METHOD TO FORM SAME 审中-公开
公开(公告)号：WO2018125204A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/069473
申请日：2016-12-30
申请人： INTEL CORPORATION
发明人： RAHMAN, MD Tofizur , WIEGAND, Christopher J. , OGUZ, Kaan , BROCKMAN, Justin S. , OUELLETTE, Daniel G. , MAERTZ, Brian , O'BRIEN, Kevin P. , DOCZY, Mark L. , DOYLE, Brian S. , GOLONZKA, Oleg , GHANI, Tahir
IPC分类号： H01L43/10 , H01L43/02 , H01L43/08 , H01L43/12
摘要： A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.

37. 发明申请

WO2018004652A1 FRONT-END TUNNEL JUNCTION DEVICE PLUS BACK-END TRANSISTOR DEVICE 审中-公开
标题翻译：前端隧道结器件加后端晶体管器件
公开(公告)号：WO2018004652A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040686
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： KUO, Charles C. , OGUZ, Kaan , DOCZY, Mark L. , DOYLE, Brian S. , O'BRIEN, Kevin P.
IPC分类号： H01L29/73 , H01L29/78 , H01L21/8238
CPC分类号： H01L27/0688 , H01L27/0617 , H01L27/0629 , H01L27/11514 , H01L27/1225 , H01L27/124 , H01L27/228 , H01L29/41733
摘要： Techniques are disclosed for forming an integrated circuit (IC) including a front-end tunnel junction device plus a back-end transistor or transistor-based device. For ease of reference, the combination of the two devices may be referred to herein as a "1T-1TJ" configuration, where the "1T" portion represents the back-end transistor or transistor-based device and the "1TJ" portion represents the front-end tunnel junction device. As will be apparent in light of this disclosure, in some embodiments, 1T-1TJ configuration can be used for memory applications, where the front-end tunnel junction device can be used as the switching element to store data (e.g., a '1' or '0') and the back-end transistor or transistor-based device can be used to write and/or read the tunnel junction switching element. Benefits can be derived from forming the tunnel junction device during front-end IC processing. Other embodiments may be described and/or disclosed.
摘要翻译：公开了用于形成包括前端隧道结器件加上后端晶体管或基于晶体管的器件的集成电路（IC）的技术。为了便于参考，这两个装置的组合可以在本文中被称为“1T-1TJ” 配置，其中“1T” 部分表示后端晶体管或基于晶体管的器件，而“1TJ” 部分代表前端隧道连接装置。根据本公开内容将显而易见的是，在一些实施例中，1T-1TJ配置可以用于存储器应用，其中前端隧道结器件可以用作开关元件以存储数据（例如'1' 或'0'），并且后端晶体管或基于晶体管的器件可以用于写入和/或读取隧道结切换元件。在前端IC处理期间形成隧道结器件可以带来好处。其他实施例可以被描述和/或公开。

38. 发明申请

WO2017171848A1 FERROMAGNETIC RESONANCE TESTING OF BURIED MAGNETIC LAYERS OF WHOLE WAFER 审中-公开
标题翻译：全晶体埋藏磁性层的铁磁共振测试
公开(公告)号：WO2017171848A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025624
申请日：2016-04-01
申请人： INTEL CORPORATION
发明人： O'BRIEN, Kevin P. , OGUZ, Kaan , WIEGAND, Christopher J , DOCZY, Mark L. , DOYLE, Brian S. , RAHMAN, MD Tofizur , GOLONZKA, Oleg , GHANI, Tahir
IPC分类号： H01L21/66 , H01L43/12 , G01R23/16 , G01R31/26
CPC分类号： G01R31/2831 , G01N24/10 , G01R31/315 , G01R33/098 , G01R33/60 , G01R35/00 , H01L22/14 , H01L43/12
摘要： Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.
摘要翻译：公开了用于在填充有一个或多个掩埋磁性层的整个晶片上执行铁磁共振（FMR）测试的技术。这些技术可用于验证或排除形成掩埋磁性层的过程，而不需要破碎晶片。基于该层的唯一频率响应，该技术还可用于将同一叠层中的一个磁层与其他磁层区分开来。一个示例性方法包括移动靠近波导（在500微米内，但没有短路）的晶片，激励目标测量点附近的DC磁场，通过波导施加RF输入信号，收集波导的频率响应的谐振频谱波导，并将谐振频谱分解成目标层的磁性。直流磁场和射频输入信号中的一个或两个可以被扫描以产生一组强大的共振谱。

39. 发明申请

WO2017171837A1 LAYER TRANSFERRED FERROELECTRIC MEMORY DEVICES 审中-公开
标题翻译：层转移铁电存储器件
公开(公告)号：WO2017171837A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025576
申请日：2016-04-01
申请人： INTEL CORPORATION
发明人： O'BRIEN, Kevin P. , DOYLE, Brian S. , OGUZ, Kaan , KUO, Charles C. , DOCZY, Mark L. , INDUKURI, Tejaswi K.
IPC分类号： H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
CPC分类号： H01L27/1159 , G11C11/221 , G11C11/223 , H01L27/11507 , H01L27/11587 , H01L29/78391
摘要： A monocrystalline metal-oxide stack including a ferroelectric (FE) tunneling layer and a buffer layer is epitaxially grown on a growth substrate. A first poly crystalline metal electrode layer is deposited over the tunneling layer. A bonding material layer is further deposited over the electrode layer. The bonding material layer is then bonded to a material layer on a front or back side of a host substrate that further comprises a transistor cell. Once bonded, the growth substrate may be removed from the metal-oxide stack to complete a transfer of the metal-oxide stack from the growth substrate to the host substrate. A second poly crystalline metal electrode layer is then deposited over the exposed buffer layer, placing both electrodes in close proximity to the FE tunneling layer.
摘要翻译：包括铁电（FE）隧穿层和缓冲层的单晶金属氧化物堆叠体在生长衬底上外延生长。在隧穿层上沉积第一多晶金属电极层。进一步在电极层上沉积结合材料层。然后将接合材料层接合到还包括晶体管单元的主基板的正面或背面上的材料层。一旦结合，可将生长衬底从金属氧化物堆叠移除以完成金属氧化物堆叠从生长衬底到主衬底的转移。然后在暴露的缓冲层上沉积第二多晶金属电极层，使两个电极紧靠FE隧穿层。

40. 发明申请

WO2017171718A1 UNIPOLAR CURRENT SWITCHING IN PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ) DEVICES THROUGH REDUCED BIPOLAR COERCIVITY 审中-公开
标题翻译：通过降低双极性校正的垂直磁隧道结（PMTJ）器件中的单极电流切换
公开(公告)号：WO2017171718A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/024573
申请日：2016-03-28
申请人： INTEL CORPORATION
发明人： KUO, Charles C. , DOCZY, Mark L. , OGUZ, Kaan , O'BRIEN, Kevin P. , DOYLE, Brian S.
IPC分类号： H01L43/02 , H01L43/10 , H01L43/12
摘要： Approaches and structures for unipolar current switching in perpendicular magnetic tunnel junction (pMTJ) devices through reduced bipolar coercivity are described. In an example, a memory array includes a plurality of bitlines and a plurality of select lines. The memory array also includes a plurality of memory elements located among and coupled to the plurality of bitlines and the plurality of select lines. Each of the plurality of memory elements includes a unipolar switching magnetic tunnel junction (MTJ) device and a select device.
摘要翻译：描述了通过降低的双极矫顽力在垂直磁隧道结（pMTJ）器件中进行单极电流开关的方法和结构。在一个示例中，存储器阵列包括多个位线和多个选择线。存储器阵列还包括位于多个位线和多个选择线之中并耦合到多个选择线的多个存储元件。多个存储器元件中的每一个包括单极开关磁隧道结（MTJ）器件和选择器件。

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