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31. 发明申请

WO2011005401A3 REDUCED PROGRAMMING PULSE WIDTH FOR ENHANCED CHANNEL BOOSTING IN NON-VOLATILE STORAGE 审中-公开
标题翻译：减少编程脉冲宽度以增强非易失性存储器的通道提升
公开(公告)号：WO2011005401A3
公开(公告)日：2011-06-30
申请号：PCT/US2010037839
申请日：2010-06-08
申请人： SANDISK CORP , DONG YINGDA , LUTZE JEFFREY W
发明人： DONG YINGDA , LUTZE JEFFREY W
IPC分类号： G11C16/10
CPC分类号： G11C16/10
摘要： Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter duration, partway through the programming operation. A switchover point can be based on temperature, selected word line position and/or tracking of storage elements to a trigger state. The switchover point occurs sooner for higher temperatures, and for drain side word lines. The trigger state can be selected based on temperature. A portion of storage elements which are required to reach the trigger state to trigger a switchover can also be set a function of temperature. Programming pulses of a shorter duration improve channel boosting for inhibited storage elements, thereby reducing program disturb for these storage elements.
摘要翻译：在编程操作期间，通过从使用较长持续时间的编程脉冲切换到较短持续时间的编程脉冲，在编程操作的中途切换，在非易失性存储系统中减少了编程干扰。切换点可以基于温度，所选字线位置和/或将存储元件跟踪到触发状态。对于较高的温度以及对于漏极侧字线，切换点更快发生。触发状态可以根据温度进行选择。达到触发状态以触发切换所需的存储元件的一部分也可以被设置为温度的函数。较短持续时间的编程脉冲改善了对禁止的存储元件的通道升压，从而减少了这些存储元件的编程干扰。

32. 发明申请

WO2011060078A1 DATA STATE-DEPENDENT CHANNEL BOOSTING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING IN MEMORY 审中-公开
标题翻译：数据状态相关通道提升降低存储器中的通道到浮动门耦合
公开(公告)号：WO2011060078A1
公开(公告)日：2011-05-19
申请号：PCT/US2010/056248
申请日：2010-11-10
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W. , SHAH, Grishma
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W. , SHAH, Grishma
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04 , G11C16/12
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3427
摘要： In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.
摘要翻译：在编程操作中，选择的字线上的所选择的存储元件被编程，同时通过通道增强来禁止所选字线上的未选择的存储元件的编程。为了提供足够但不是过高的升压水平，可以基于未选择的存储元件的数据状态来设定升压量。可以为代表较低阈值电压的较低数据状态提供更大量的升压，因此更易受编程干扰的影响。一个共同的升压方案可以用于多个数据状态的组。可以通过调整用于通道预充电操作的电压的时序和幅度以及施加到字线的通过电压来设置升压量。在一种方法中，可以使用未选择字线上的阶梯式通过电压来调整具有所选数据状态的通道的升压。

33. 发明申请

WO2010002879A1 CORRECTING FOR OVER PROGRAMMING NON-VOLATILE STORAGE 审中-公开
标题翻译：更正编程非易失性存储
公开(公告)号：WO2010002879A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/049238
申请日：2009-06-30
申请人： SANDISK CORPORATION , LUTZE, Jeffrey, W. , LI, Yan
发明人： LUTZE, Jeffrey, W. , LI, Yan
IPC分类号： G11C16/34 , G11C16/16 , G11C11/56
CPC分类号： G11C16/3404 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/3413 , G11C16/3463
摘要： A non-volatile storage system corrects over programmed memory cells by selectively performing one or more erase operations on a subset of non-volatile storage elements that are connected to a common word line (or other type of control line).
摘要翻译：非易失性存储系统通过在连接到公共字线（或其他类型的控制线）的非易失性存储元件的子集上选择性地执行一个或多个擦除操作来校正编程的存储器单元。

34. 发明申请

WO2009146235A4 COMPENSATING NON-VOLATILE STORAGE USING DIFFERENT PASS VOLTAGES DURING PROGRAM- VERIFY AND READ 审中-公开
公开(公告)号：WO2009146235A4
公开(公告)日：2009-12-03
申请号：PCT/US2009/042564
申请日：2009-05-01
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W.
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W.
IPC分类号： G11C16/04 , G11C16/34
摘要： Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine.

35. 发明申请

WO2005015566A8 DETECTING OVER PROGRAMMED MEMORY 审中-公开
标题翻译：检测编程的存储器
公开(公告)号：WO2005015566A8
公开(公告)日：2007-09-07
申请号：PCT/US2004021254
申请日：2004-06-30
申请人： SANDISK CORP , CHEN JIAN , LI YAN , LUTZE JEFFREY W
发明人： CHEN JIAN , LI YAN , LUTZE JEFFREY W
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3463 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C16/3459
摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.
摘要翻译：在非易失性半导体存储器系统（或其他类型的存储器系统）中，通过改变该存储器单元的阈值电压对存储器单元进行编程。由于系统中不同存储器单元的编程速度的变化，存在一些存储器单元将被过度编程的可能性。也就是说，在一个示例中，阈值电压将被移动超过预期值或值的范围。本发明包括确定存储器单元是否被过度编程。

36. 发明申请

WO2006132818A3 STARTING PROGRAM VOLTAGE SHIFT WITH CYCLING OF NON-VOLATILE MEMORY 审中-公开
标题翻译：启动具有非易失性存储器循环的程序电压转换
公开(公告)号：WO2006132818A3
公开(公告)日：2007-07-12
申请号：PCT/US2006020375
申请日：2006-05-26
申请人： SANDISK CORP , LUTZE JEFFREY W
发明人： LUTZE JEFFREY W
IPC分类号： G11C16/10
CPC分类号： G11C16/12 , G11C16/0483
摘要： A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.
摘要翻译：公开了一种用于编程非易失性存储器的系统，其通过将起始编程电压设置为新鲜部件的第一电平并在存储器循环时调整起始编程电压来提高性能。例如，该系统使用具有第一初始值的增加的程序信号在第一时段期间对一组非易失性存储元件进行编程，并且随后使用增加的程序信号在第二周期期间对该组非易失性存储元件进行编程，第二初始值，其中第二周期在第一周期之后且第二初始值不同于第一初始值。

37. 发明申请

WO2005081318A1 SHIELD PLATE FOR LIMITING CROSS COUPLING BETWEEN FLOATING GATES 审中-公开
标题翻译：用于限制浮动闸门之间的交叉耦合的屏蔽板
公开(公告)号：WO2005081318A1
公开(公告)日：2005-09-01
申请号：PCT/US2005/004157
申请日：2005-02-09
申请人： SANDISK CORPORATION , MOKHLESI, Nima , LUTZE, Jeffrey, W.
发明人： MOKHLESI, Nima , LUTZE, Jeffrey, W.
IPC分类号： H01L27/115
CPC分类号： G11C11/5642 , G11C11/5628 , G11C2211/5621 , H01L27/115 , H01L27/11521 , H01L29/7887
摘要： A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned between adjacent floating gate stacks and electrically connected to the source/drain regions for reducing coupling between adjacent floating gates. The shield plates are selectively grown on the active areas of the memory without being grown on the inactive areas. In one embodiment, the shield plates are epitaxially grown silicon positioned above the source/drain regions.
摘要翻译：公开了一种包括一组非易失性存储元件的存储器系统。所述非易失性存储元件中的每一个包括在衬底中的沟道的相对侧处的源极/漏极区域和在沟道上方的浮动栅极堆叠。存储器系统还包括位于相邻浮置栅极堆叠之间并且电连接到源极/漏极区域的一组屏蔽板，用于减少相邻浮动栅极之间的耦合。屏蔽板选择性地生长在存储器的有效区域上，而不会在非活动区域上生长。在一个实施例中，屏蔽板是位于源极/漏极区上方的外延生长的硅。

38. 发明申请

WO2012012261A1 PROGRAMMING NON-VOLATILE MEMORY WITH BIT LINE VOLTAGE STEP UP 审中-公开
标题翻译：编程具有位线电压升压的非易失性存储器
公开(公告)号：WO2012012261A1
公开(公告)日：2012-01-26
申请号：PCT/US2011/044016
申请日：2011-07-14
申请人： SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , LUTZE, Jeffrey, W.
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W.
IPC分类号： G11C11/56 , G11C16/34 , G11C16/24 , G11C16/12
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C16/3454 , G11C16/3486 , G11C2216/14
摘要： Threshold voltage distributions (A, B, C) in a non-volatile memory device(196) are norrowed, and/or programming time is reduced, using a programming technique in which the bit line voltage for storagr elements having a target data state (402,404,406) is stepped up, in lock step with a step up in the program voltage. The step up in the bit line voltage is performed at different times in the programming pass, for different subsets of storage elements, according to their target data state (402, 404, 406). The start and stop of the step up in the bit line voltage (Vbc) can be set based on a fixed program pulse number, or adaptive based on a programming progress. Variations include using a fixed bit line step, a varying bit line step, a data state- dependent bit line step, an option to not step up the bit line for one or more data states and an option to add an additional bit line bias.
摘要翻译：使用编程技术对非易失性存储器件（196）中的阈值电压分布（A，B，C）进行解调和/或编程时间减少，其中存储器元件的位线电压具有目标数据状态（ 402,404,406）被升压，在锁定步骤中升高编程电压。根据它们的目标数据状态（402,404,406），针对存储元件的不同子集，在编程遍历中的不同时间，对位线电压进行升压。可以基于固定的编程脉冲数或基于编程进度的自适应来设置位线电压（Vbc）中的升压的开始和停止。变化包括使用固定位线步长，变化位线步长，数据状态相关位线步长，不增加一个或多个数据状态的位线的选项以及添加附加位线偏置的选项。

39. 发明申请

WO2010044993A1 MULTI-PASS PROGRAMMING FOR MEMORY USING WORD LINE COUPLING 审中-公开
标题翻译：使用字线耦合的存储器的多通道编程
公开(公告)号：WO2010044993A1
公开(公告)日：2010-04-22
申请号：PCT/US2009/057984
申请日：2009-09-23
申请人： SANDISK CORPORATION , DUTTA, Deepanshu , LUTZE, Jeffrey, W.
发明人： DUTTA, Deepanshu , LUTZE, Jeffrey, W.
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3418 , G11C16/3454 , G11C2211/5621 , G11C2211/5648
摘要： A multiple pass programming scheme is optimized using capacitive coupling in the word line to word line direction during program-verify operations. A different pass voltage is used in different programming passes on an adjacent word line of a selected word line which is being verified. In particular, a lower pass voltage can be used in a first pass than in a second pass. The programming process may involve a word line look ahead or zigzag sequence in which WLn is programmed in a first pass, followed by WLn+ 1 in a first pass, followed by WLn in a second pass, followed by WLn+1 in a second pass. An initial programming pass may be performed before the first pass in which storage elements are programmed to an intermediate state and/or to a highest state.
摘要翻译：在编程验证操作期间，使用字线到字线方向的电容耦合来优化多通道编程方案。在正在验证的所选字线的相邻字线上的不同编程遍中使用不同的通过电压。特别地，可以在第一遍中比在第二遍中使用较低通过电压。编程过程可以包括字线前视或之字形序列，其中WLn在第一遍中编程，其次是第一遍中的WLn + 1，之后是第二遍中的WLn，之后是第二遍中的WLn + 1。可以在其中存储元件被编程到中间状态和/或最高状态的第一遍之前执行初始编程遍。

40. 发明申请

WO2009042345A1 NAND STRINGS WITH OFFSET CHARGE STORAGE LAYERS AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有偏置电荷存储层的NAND带及其制造方法
公开(公告)号：WO2009042345A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/074641
申请日：2008-08-28
申请人： SANDISK CORPORATION , LUTZE, Jeffrey, W. , LEE, Dana
发明人： LUTZE, Jeffrey, W. , LEE, Dana
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/1158 , H01L27/11524 , H01L27/11553 , H01L27/11568 , H01L27/1157
摘要： A plurality of non- volatile storage elements on a common active layer are offset from neighbor non- volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements. For example, a NAND string over active area (100) has a charge storage nitride layer (112) that is vertically offset to the charge storage layer (112) of the NAND string over active area (202).
摘要翻译：公共活动层上的多个非易失性存储元件偏离邻近非易失性存储元件。非易失性存储元件的这种抵消有助于减少邻近非易失性存储元件的干扰。还描述了制造偏移非易失性存储元件的制造方法。例如，有源区（100）上的NAND串具有电荷存储氮化物层（112），其在有源区（202）上垂直偏移到NAND串的电荷存储层（112）。

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