专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

WO2008032782A1 増幅装置、出力制御方法、および制御プログラム审中-公开
标题翻译：放大单元，输出控制方法和控制程序
公开(公告)号：WO2008032782A1
公开(公告)日：2008-03-20
申请号：PCT/JP2007/067836
申请日：2007-09-13
申请人：日本電気株式会社 , 野瀬浩一 , 石崎晴也 , 水野正之
发明人：野瀬浩一 , 石崎晴也 , 水野正之
IPC分类号： H03K4/02 , H03F3/24 , H03F3/68 , H03K4/92 , H03K5/02
CPC分类号： H03K4/026 , H03F1/0294 , H03F1/32 , H03F3/2171 , H03F3/2178 , H03F3/245 , H03F3/72 , H03F2200/384 , H03K4/92
摘要：【課題】　低電圧、低電力で動作可能で、高調波成分の発生を有効に抑制したパルス入力型のパワー増幅装置等を提供する。【解決手段】　出力側が相互に接続され同一周波数で駆動する複数の増幅器から成る一方と他方の少なくとも二つの増幅回路１１，１２を設ける。一方の増幅回路１２を構成する複数の増幅器を、基準パルス２３を入力し増幅する第１の反転増幅器Ｍ１１と、基準パルス２３の位相をずらし且つ反転してなる反転パルス２２を入力する反転増幅器Ｍ１２とにより構成する。そして、前記他方の増幅回路１１を、前記基準パルス２３よりもパルス幅の広い他の幅広パルス２１を共通に入力する第１の反転増幅器Ｍ１４と反転増幅器Ｍ１３とにより構成する。
摘要翻译：为了提供例如能够以低电压和低功率工作的脉冲输入型功率放大单元，能够有效地抑制谐波成分的产生。解决问题的手段放大单元设置有至少两个放大电路，由具有彼此连接的输出侧的多个放大器组成的一个和另外的放大电路（11,12）以相同的频率工作。构成一个放大电路（12）的多个放大器由输入参考脉冲（23）的第一反相放大器（M11）构成并放大输入由相移产生的反相脉冲（22）的相同和反相放大器（M12），并且参考脉冲（23）的反转。另一个放大电路（11）由反向放大器（M13）和第一反相放大器（M14）构成，共同输入宽度大于参考脉冲（23）宽度的其他宽脉冲（21）。

22. 发明申请

WO2006051054A3 AMPLIFYING CIRCUIT AND METHOD FOR CORRECTING THE PULSE DUTY FACTOR OF A DIFFERENTIAL CLOCK SIGNAL 审中-公开
标题翻译：放大器电路和用于校正差分时钟信号的连续比率的方法
公开(公告)号：WO2006051054A3
公开(公告)日：2006-08-17
申请号：PCT/EP2005055691
申请日：2005-11-02
申请人： INFINEON TECHNOLOGIES AG , HEYNE PATRICK
发明人： HEYNE PATRICK
IPC分类号： H03K5/00 , H03K5/02 , H03K5/151 , H03K5/156 , H03K5/24
CPC分类号： H03K5/2481 , H03K5/151 , H03K5/1565 , H03K2005/00228
摘要： The invention relates to an amplifying circuit and to a method for correcting the pulse duty factor of a differential clock signal (CLt, CLc) to give a desired value of 50 % using a differential amplifier (1) having an MOS transistor pair (T1, T2). According to said method, the clock signal (CLt, CLc) to be corrected is applied to the respective gate of the MOS transistor pair (T1, T2), and a differential analog pulse duty correction signal (DCt, DCc) is produced by respective integration of the true and complementary clock signal (ACLt, ACLc) emitted by every MOS transistor (T1, T2) of the differential amplifier (1) on its source/drain connection. The differential pulse duty correction signal (DCt, DCc) thereby obtained is applied to the respective electrically insulated substrate connections (S1, S2) of the MOS transistor pair (T1, T2) so that the substrate voltages and the cutoff voltages of the MOS transistors (T1, T2) of the transistor pair are influenced in the opposite direction.
摘要翻译：本发明涉及一种放大器电路和用于通过一对MOS晶体管的装置校正的差分时钟信号（CLT，CLC），其具有50％的所期望的值的占空比的方法（TL，T2）差动放大器（1）。在这种情况下，待校正的时钟信号（CLT，CLC）被提供给MOS晶体管对（T1中，T2）中的相应的栅极端子施加，差分模拟Tastverhältniskorrektursignals（DCT DCC）通过的各MOS晶体管的各自的积分（TL，T2）传递到其源极/漏极中产生（1）真和互补的时钟信号（ACLT，ACLC）差动放大器，因此产生（DCT DCC）的差动Tastverhältniskorrektursignals的终端（在每种情况下，MOS晶体管对的电分离基板端子（SL，S2）T1中， T2），使得在每种情况下，晶体管对的MOS晶体管（T1，T2）的衬底电压以及因此的阈值电压在相反的方向上受到影响。

23. 发明申请

WO2005101660A1 VOLTAGE LIMITED SYSTEMS AND METHODS 审中-公开
标题翻译：电压有限系统和方法
公开(公告)号：WO2005101660A1
公开(公告)日：2005-10-27
申请号：PCT/US2005/012361
申请日：2005-04-12
申请人： ADVANCED NEUROMODULATION SYSTEMS, INC.
发明人： VARRICHIO, Anthony, J. , TRANCHINA, Benjamin, A.
IPC分类号： H03K5/02
CPC分类号： H02M3/073 , A61N1/36125 , A61N1/36153 , A61N1/3782 , H02M3/07 , H02M2003/072
摘要： In delivering constant current electrical stimulation pulses to electrodes implanted near a stimulation site, a programmable voltage limited mode of operation according to embodiments precludes unsafe voltage spikes upon substantial changes in resistance due to, for example, patient movement. A voltage multiplier of one embodiment is driven by a clock signal stopped whenever an output voltage reaches a predetermined level, and resumed when the output voltage drops below that level. A compurgator receiving a voltage-divided output from the voltage multiplier and a variable input control signal from a digital-to-analog converter controls generation of the clock signal according to embodiments.
摘要翻译：在将恒定的电刺激脉冲传送到植入在刺激部位附近的电极的情况下，根据实施例的可编程电压限制操作模式排除了由于例如患者运动导致的电阻显着变化时的不安全电压尖峰。一个实施例的电压倍增器由输出电压达到预定电平时停止的时钟信号驱动，并且当输出电压下降到该电平以下时恢复。接收来自电压倍增器的分压输出的加压器和来自数模转换器的可变输入控制信号根据实施例控制时钟信号的产生。

24. 发明申请

WO2005011104A3 LOW-CONSUMPTION VOLTAGE AMPLIFIER 审中-公开
标题翻译：低消耗电压放大器
公开(公告)号：WO2005011104A3
公开(公告)日：2005-03-31
申请号：PCT/FR2004050330
申请日：2004-07-13
申请人： COMMISSARIAT ENERGIE ATOMIQUE , ARQUES MARC
发明人： ARQUES MARC
IPC分类号： H03F1/02 , H03F1/22 , H03F1/30 , H03F3/08 , H03F3/193 , H03F3/345 , H03K5/02
CPC分类号： H03F3/087 , H03F1/0205 , H03F1/223 , H03F1/301 , H03F3/193 , H03F3/345 , H03F2200/48 , H03F2200/78
摘要： The invention relates to a low-consumption voltage amplifier. Said amplifier comprises a transistor (M1), a first current generator (I1), supplying the transistor's (M1) drain, a second current generator (I0), charging the transistor's (M1) source, the current provided by the second current generator (I1) being substantially equal to the current provided by the first current generator (I0), a first capacitor (C1), connected to the transistor's (M1) drain and a second capacitor (C0), connected to the transistor's (M1) source. An additional field effect transistor (M3), of a type opposite to that of the first field effect transistor, is arranged between the current generator (I1) and the first field effect transistor (M1). Said invention applies more particularly to the voltage amplification of a X-ray or gamma-ray detector.
摘要翻译：本发明涉及一种低功耗电压放大器。所述放大器包括晶体管（M1），提供晶体管（M1）漏极的第一电流发生器（I1），向晶体管（M1）源充电第二电流发生器（I0）的第二电流发生器（I0） I1）基本上等于由第一电流发生器（I0）提供的电流，连接到晶体管（M1）漏极的第一电容器（C1）和连接到晶体管（M1）源极的第二电容器（C0）。在电流发生器（I1）和第一场效应晶体管（M1）之间设置与第一场效应晶体管相反的类型的附加场效应晶体管（M3）。本发明更具体地适用于X射线或γ射线检测器的电压放大。

25. 发明申请

WO00077931A1 AMPLIFIER 审中-公开
标题翻译：放大器
公开(公告)号：WO00077931A1
公开(公告)日：2000-12-21
申请号：PCT/EP2000/003629
申请日：2000-04-20
IPC分类号： H03F1/26 , H03F3/195 , H03F3/30 , H03K5/02 , H03F3/345 , H03K19/00
CPC分类号： H03F3/3028 , H03F1/26 , H03F2200/372
摘要： An amplifier circuit comprises a circuit input (14), and a circuit output (22). An inverter, comprising first and second MOS transistors (16, 18) is connected between first and second supply voltages (Vdd, Vss), and has an inverter input connected to the circuit input (14), and an inverter output (20), which provides an inverter output current corresponding to a circuit input voltage. A first resistive element comprises a third MOS transistor (24) and a fourth MOS transistor (26), the third and fourth transistors being of opposite conductivity types, and each having their gate and drain terminals connected to the inverter output (20) and the circuit output (22), and having their respective source terminals connected to respective ones of the first and second supply voltages (Vdd, Vss). A second resistive element comprises a fifth MOS transistor (30) and a sixth MOS transistor (32), the fifth and sixth transistors being of opposite conductivity types, and each having its drain-source path connected between the circuit output (22) and the circuit input (14), and having its gate connected to a respective voltage source (34, 36). The amplifier circuit is suitable for integration using CMOS techniques, and for use at radio frequencies, while providing good performance in terms of its noise figure. Alternative embodiments are disclosed having various combinations of the above components.
摘要翻译：放大器电路包括电路输入端（14）和电路输出端（22）。包括第一和第二MOS晶体管（16,18）的反相器连接在第一和第二电源电压（Vdd，Vss）之间，并且具有连接到电路输入端（14）的反相器输入端和反相器输出端（20），其提供对应于电路输入电压的逆变器输出电流。第一电阻元件包括第三MOS晶体管（24）和第四MOS晶体管（26），第三和第四晶体管具有相反的导电类型，并且其栅极和漏极端子连接到逆变器输出端（20），并且电路输出（22），并且其各自的源极端子连接到第一和第二电源电压（Vdd，Vss）中的相应的一个。第二电阻元件包括第五MOS晶体管（30）和第六MOS晶体管（32），第五和第六晶体管具有相反的导电类型，并且其漏极源路径连接在电路输出端（22）和电路输入（14），并且其栅极连接到相应的电压源（34,36）。放大器电路适用于使用CMOS技术的集成，并且在无线电频率下使用，同时在其噪声系数方面提供良好的性能。公开了具有上述组件的各种组合的替代实施例。

26. 发明申请

WO98035444A1 HIGH-VOLTAGE CMOS LEVEL SHIFTER 审中-公开
标题翻译：高电压CMOS电平变换器
公开(公告)号：WO98035444A1
公开(公告)日：1998-08-13
申请号：PCT/US1998/001298
申请日：1998-01-23
IPC分类号： H03K5/02 , H03K3/356 , H03K17/10 , H03K19/0185
CPC分类号： H03K17/102 , H03K3/356113
摘要： A high-voltage level shifter includes one or more complementary NMOS/PMOS series intermediate transistor pairs (MP1, MN1) to divide the high-voltage supply range into two or more sub-ranges. The level shifter has a differential structure with complementary NMOS input transistors (MNI, M'NI). Cross-coupled PMOS output transistors (MPO, M'PO) provide complementary outputs. The complementary NMOS/PMOS series intermediate transistor pairs separate the NMOS input transistor drains from the PMOS output transistor drains. In order to divide the high voltage range into h subranges, h-1 complementary NMOS/PMOS series intermediate transistor pairs are used each being biased by monotonically increasing fixed intermediate voltages. In a shared-bias embodiment, each complementary NMOS/PMOS series intermediate transistor pair is biased by a single corresponding intermediate voltage. In a split-bias embodiment, each complementary NMOS/PMOS series intermediate transistor pair is biased by a corresponding NMOS bias voltage and a corresponding PMOS bias voltage, in which the NMOS bias voltage is higher than the PMOS bias voltage by the sum or the NMOS threshold voltage and the PMOS threshold voltage. In another aspect, the N-wells of the PMOS transistors are tied to an upwardly vertically adjacent intermediate voltage in the shared-bias embodiments, and are tied to an upwardly vertically adjacent NMOS bias voltage in the split-bias embodiments. In a twin tub embodiment for very high voltage applications, the P-wells of the NMOS transistors are tied to a downwardly vertically adjacent intermediate voltage in the shared-bias embodiments, and are tied to a downwardly vertically adjacent PMOS bias voltage for the split-bias embodiments.
摘要翻译：高压电平移位器包括一个或多个互补的NMOS / PMOS串联中间晶体管对（MP1，MN1），以将高电压电源范围分成两个或更多个子范围。电平移位器具有互补NMOS输入晶体管（MNI，M'NI）的差分结构。交叉耦合PMOS输出晶体管（MPO，M'PO）提供互补输出。互补的NMOS / PMOS系列中间晶体管对将NMOS输入晶体管漏极与PMOS输出晶体管漏极分离。为了将高电压范围划分为h个子范围，使用h-1互补的NMOS / PMOS系列中间晶体管对，通过单调增加固定中间电压来偏置。在共享偏置实施例中，每个互补NMOS / PMOS系列中间晶体管对由单个对应的中间电压偏置。在分离偏置实施例中，每个互补NMOS / PMOS串联中间晶体管对由相应的NMOS偏置电压和相应的PMOS偏置电压偏置，其中NMOS偏置电压高于PMOS偏置电压乘以和或NMOS 阈值电压和PMOS阈值电压。在另一方面，PMOS晶体管的N阱在共享偏压实施例中被连接到向上垂直相邻的中间电压，并且在分离偏压实施例中被连接到向上垂直相邻的NMOS偏置电压。在用于非常高电压应用的双槽实施例中，NMOS晶体管的P阱在共享偏压实施例中被连接到向下垂直相邻的中间电压，并且被连接到用于分离电压的向下垂直相邻的PMOS偏置电压，偏压实施例。

27. 发明申请

WO9217938A3 DIFFERENTIAL DRIVER/RECEIVER CIRCUIT 审中-公开
标题翻译：差分驱动器/接收器电路
公开(公告)号：WO9217938A3
公开(公告)日：1993-10-14
申请号：PCT/US9202466
申请日：1992-03-27
申请人： THINKING MACHINES CORP
发明人： WADE JON P , WELLS DAVID S
IPC分类号： H03K3/356 , H03K5/02 , H03K17/16 , H03K17/687 , H03K17/693 , H03K19/003 , H04B3/50 , H04L25/02 , H04L25/03 , H03K
CPC分类号： H04L25/028 , H03K3/356147 , H03K5/023 , H03K17/164 , H03K17/693 , H04L25/0272 , H04L25/0292 , H04L25/03834
摘要： A new driver circuit and receiver circuit for transmitting and receiving a differential signal pair. The driver circuit includes true and complement signal generating elements that generate a differential signal pair in tandem. Each of the true and complement signal generating elements includes a high-gain element and at least one low-gain element. The delay circuit is responsive to the true and complement data signal for iteratively controlling the high-gain element and low-gain element of each signal generating element to effect the generation of the differential signal pair, the delay circuit controlling the high-gain element with a delay relative to the low-gain element to thereby reduce ringing in the differential signal pair. The receiver circuit receives a differential receive signal pair, comprising true and complement receive signals having selected conditions over a pair of input lines and generates a true and complement data signal. The receiver circuit, during normal receiving operations, generates true and complement signals in response to the differential receive signal pair. During a test mode, the receiver circuit, in separate steps, compares the voltage levels of the true and complement receive signals to threshold voltages and generates an error signal if the selected true or complement receive signal does not have the proper relationship to the voltage level of the threshold voltage.

28. 发明申请

WO8809034A3 SENSE AMPLIFIER 审中-公开
标题翻译：感应放大器
公开(公告)号：WO8809034A3
公开(公告)日：1989-01-12
申请号：PCT/US8703277
申请日：1987-12-10
申请人： ANALOG DEVICES INC
发明人： GARDE DOUGLAS
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409 , H03K5/02 , H03K5/24 , H03K19/0948
CPC分类号： G11C7/062 , H03K5/2481
摘要： A MOS sense amplifier having a differential input and a single-ended output, and formed of only six MOS transistors. The amplifier's non-inverting input is connected to the gates of first and second MOSFETs. The drains of the first and second MOSFETs are connected to each other and to the gates of third and fourth MOSFETs. The drain of the third MOSFET is connected to the sources of the second and sixth MOSFETs; and the source of the third MOSFET is connected to the positive supply voltage. The drain of the fourth MOSFET is connected to the sources of the first and fifth MOSFETs. The source of the fourth MOSFET is connected to ground. The inverting input of the sense amplifier is connected to the gates of the fifth and sixth MOSFETs. The drains of the fifth and sixth MOSFETs are connected to each other and provide the output terminus of the amplifier. The first, fourth and fifth MOSFETs are n-channel devices, while the second, third and sixth MOSFETs are p-channel devices.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式