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11. 发明申请

WO1997009788A2 A/D CONVERSION WITH FOLDING AND INTERPOLATION 审中-公开
标题翻译： A / D转换与折叠和插值
公开(公告)号：WO1997009788A2
公开(公告)日：1997-03-13
申请号：PCT/IB1996000869
申请日：1996-08-29
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , VORENKAMP, Pieter , VENES, Arnoldus, Gerardus, Wilhelmus , VAN DE PLASSCHE, Rudy, Johan
IPC分类号： H03M01/34
CPC分类号： H03M1/204 , H03M1/141
摘要： An A/D converter has an input part IS which provides transitions T1..Tx associated with different levels of an analog input signal Vin. An intermediate part IMS carries out folding and interpolation operations F1, I1 and F2, I2..IN on the transitions T1..Tx to obtain a set of bit-determining signals XO.. XQ. At least one of the operations, folding F1, F2,.. or interpolation I1, IN, is carried out more than once in alternation with the other operation, interpolation I1, IN or folding F1, F2,.. respectively. An output part OS provides a digital output signal Do on the basis of the bit-determining signals XO..XQ. Such an A/D converter can be implemented in a cost-efficient manner and may be combined with digital signal-processing circuitry.
摘要翻译： A / D转换器具有输入部分IS，其提供与模拟输入信号Vin的不同电平相关联的转换T1..Tx。中间部分IMS在转变T1..Tx上执行折叠和内插操作F1，I1和F2，I2..IN，以获得一组位确定信号XO .. XQ。与其他操作，插补I1，IN或折叠F1，F2，...分别交替执行多次折叠F1，F2或..或插值I1，IN的操作中的至少一个。输出部分OS基于比特确定信号XO ... XQ提供数字输出信号Do。这样的A / D转换器可以以成本有效的方式实现，并且可以与数字信号处理电路组合。

12. 发明申请

WO9709787A2 SIGNAL PROCESSING WITH SAMPLING 审中-公开
标题翻译：信号处理采样
公开(公告)号：WO9709787A2
公开(公告)日：1997-03-13
申请号：PCT/IB9600886
申请日：1996-09-02
申请人： PHILIPS ELECTRONICS NV , PHILIPS NORDEN AB
发明人： VAN DE PLASSCHE RUDY JOHAN , VENES ARNOLDUS GERARDUS WILHEL
IPC分类号： H03M1/12 , H03M1/00 , H03M1/36
CPC分类号： H03M1/1245 , H03M1/141 , H03M1/203
摘要： In a signal-processing arrangement, a conversion circuit CONV converts an input signal Sin into sub-ranging signals Sc(1)..Sc(N) associated with different amplitude sub-ranges. Sampling circuits SC(1)..SC(N) supply sampled portions of the sub-ranging signals Sc(1)..Sc(N) to a processing circuit PROC. The aforementioned operations may form part of an A/D conversion. The signal-processing arrangement is particularly suitable for use in a receiver, a multimedia apparatus and various types of disc-players and tape-recorders.
摘要翻译：在信号处理装置中，转换电路CONV将输入信号Sin转换为与不同振幅子范围相关的子范围信号Sc（1）... Sc（N）。采样电路SC（1）... SC（N）将子测距信号Sc（1）... Sc（N）的采样部分提供给处理电路PROC。上述操作可能构成A / D转换的一部分。信号处理装置特别适用于接收机，多媒体装置以及各种类型的盘播放器和录像机。

13. 发明申请

WO1992008288A1 ANALOG TO DIGITAL CONVERTER WITH DOUBLE FOLDING INTERPOLATION CIRCUITRY 审中-公开
标题翻译：模拟到具有双折叠插值电路的数字转换器
公开(公告)号：WO1992008288A1
公开(公告)日：1992-05-14
申请号：PCT/US1991008230
申请日：1991-11-05
申请人： SIGNAL PROCESSING TECHNOLOGIES, INC.
发明人： SIGNAL PROCESSING TECHNOLOGIES, INC. , SCHMIDT, Robert, Roy , MOSCOVICI, Alfi
IPC分类号： H03M01/56
CPC分类号： H03M1/203 , H03M1/141
摘要： An analog to digital converter (ADC) (10) having a coarse converter (12) to generate the most significant bits of the output and double folding interpolation circuitry (20) to generate the least significant bits. Each side of the double folding circuit includes additional folding stages (26, 28) coupled to reference voltages above and below the full scale input range of the ADC to cancel offset errors and improve circuit linearity. The interpolation circuit (30) includes one interpolation stage (32), having two multiplier networks (310, 320), for each least significant bit. Each interpolation stage receives two pairs of signals from the preceding stage and outputs two pairs of signals to the next stage. One of the pairs of output signals from each interpolation stage is also sent to a latched comparator (42). The outputs of all of the latched comparators can be read directly as the ADC output bits without requiring a decoder.

14. 发明申请

WO2013134988A1 一种基于功率谱估计的信号预测折叠内插ADC方法审中-公开
公开(公告)号：WO2013134988A1
公开(公告)日：2013-09-19
申请号：PCT/CN2012/074368
申请日：2012-04-19
申请人：西安交通大学 , 张春茗 , 邵志标 , 张文莲
发明人：张春茗 , 邵志标 , 张文莲
IPC分类号： H03M1/12
CPC分类号： H03M1/208 , H03M1/141
摘要：一种基于功率谱估计的信号预测折叠内插ADC方法，包括 N F = N coarse + N fine 位流水线折叠插值ADC、基于功率谱估计的信号预测单元、数模转换器和减法单元；所述流水线折叠插值ADC包括前端单个采样保持电路、分布式采样保持电路、模拟折叠预处理电路、细量化ADC和粗量化ADC；SDR接收系统模拟前端的ADC的输入信号 x（t）由来自不同标准、波段、模式的经ADC模拟前端处理的调制信号组成， x（t）覆盖不同的频谱并且具有不同的信号功率。本方案解决了ADC的精度和速度边界问题，提升ADC的输入动态范围，满足SDR接收机对高性能ADC的要求。

15. 发明申请

WO2010033232A4 UNIFIED ARCHITECTURE FOR FOLDING ADC 审中-公开
标题翻译：用于折叠ADC的统一架构
公开(公告)号：WO2010033232A4
公开(公告)日：2010-08-26
申请号：PCT/US2009005225
申请日：2009-09-18
申请人： NAT SEMICONDUCTOR CORP , TAFT ROBERT CALLAGHAN
发明人： TAFT ROBERT CALLAGHAN
IPC分类号： H03M1/12
CPC分类号： H03M1/141
摘要： A system, apparatus and method for a folding analog-to-digital converter (ADC) are described. The general architecture of the folding ADC includes an array (1 - N) of cascaded folding amplifier stages, a distributed array of fine comparators, and an encoder. Each folding amplifier stage includes folding amplifiers that are configured to receive inputs from a prior stage, and also generate output signals for the next stage. The folding amplifiers output signals for a given stage are evaluated by a corresponding comparator stage, which may include multiple comparators, and also optionally coupled to an interpolator. The outputs of the comparators from all stages are collectively evaluated by the encoder, which generates the output of the folding ADC. Unlike conventional folding ADCs that require fine and coarse channels, the presently described folding ADC provides conversion without the need for a coarse channel. The encoder can also be arranged to facilitate recursive error correction.
摘要翻译：描述了用于折叠模数转换器（ADC）的系统，装置和方法。折叠ADC的通用架构包括一个级联折叠放大器级（1 - N），一个精细比较器的分布式阵列和一个编码器。每个折叠放大器级包括折叠放大器，其被配置为接收来自前一级的输入，并且还生成用于下一级的输出信号。用于给定级的折叠放大器输出信号由相应的比较器级评估，该比较器级可以包括多个比较器，并且还可选地耦合到内插器。来自所有级的比较器的输出由编码器集中评估，编码器生成折叠式ADC的输出。与需要精细和粗糙通道的传统折叠ADC不同，目前描述的折叠式ADC提供转换而不需要粗糙通道。编码器也可以安排为便于递归纠错。

16. 发明申请

WO2007000423A1 CIRCUIT ELECTRONIQUE A RESEAU DE PAIRES DIFFERENTIELLES DISYMETRIQUES 审中-公开
标题翻译：电子网络电路与对称差分对
公开(公告)号：WO2007000423A1
公开(公告)日：2007-01-04
申请号：PCT/EP2006/063518
申请日：2006-06-23
申请人： ATMEL GRENOBLE , BORE, François , BRUEL, Sandrine , WINGENDER, Marc
发明人： BORE, François , BRUEL, Sandrine , WINGENDER, Marc
IPC分类号： H03F3/45
CPC分类号： H03F3/45744 , H03F3/45085 , H03F3/45596 , H03F2203/45032 , H03F2203/45371 , H03M1/0607 , H03M1/141 , H03M1/362
摘要： L'invention concerne les circuits intégrés comportant un ensemble de paires différentielles identiques de deux transistors chacune (T1 , T2 ; T3, T4) dont l'un reçoit sur sa base une tension variable (Vinp, Vinn) et dont l'autre reçoit sur sa base une tension de référence fixe (Vrefp, Vrefn). Pour réduire la dispersion des tensions d'offset de ces paires différentielles, on prévoit que le transistor (T2, T4) qui reçoit une tension de référence fixe a une surface d'émetteur au moins deux fois plus grande que le transistor (T1 , T3) qui reçoit sur sa base une tension variable. Application aux circuits à repliement de signal et aux convertisseurs analogiques-numériques utilisant des paires différentielles de transistors.
摘要翻译：本发明涉及集成电路，其包括一组相同的差分对的两个晶体管（T1，T2; T3，T4），一组在其基极上接收可变电压（Vinp，Vinn），另一个接收固定的参考电压（Vrefp，Vrefn）。为了减小所述差分对的偏移电压的偏差，接收固定参考电压的晶体管（T2，T4）的发射表面至少是接收可变电压的晶体管（T1，T3）的两倍在其基础上。本发明适用于使用差分对晶体管的混叠电路和模数转换器。

17. 发明申请

WO2005011125A1 CROSS-COUPLED FOLDING CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER PROVIDED WITH SUCH A FOLDING CIRCUIT 审中-公开
标题翻译：交叉耦合折叠电路和模拟数字转换器，提供了一个折叠电路
公开(公告)号：WO2005011125A1
公开(公告)日：2005-02-03
申请号：PCT/IB2004/051289
申请日：2004-07-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SCHOLTENS, Peter, C., S.
发明人： SCHOLTENS, Peter, C., S.
IPC分类号： H03M1/36
CPC分类号： H03M1/141
摘要： A cross coupled folding circuit comprises a reference voltage circuit to supply m reference voltages, an amplifier circuit to provide control signals, in response to an input signal and to the reference voltages and 2 n - I three times cross coupled folding circuits, each of which comprising three differential transistor pairs, said differential transistors pairs being controlled by said control signals and active in a voltage range around a respective one of said reference voltages, with m = 3(2"- 1). In cascade with said 2 n - I folding circuits, there are differential transistor pairs in n-1 successive steps 2 n-1 , 2 n_2 , , 2 ° . To obtain complete folding, switching circuits are provided, cooperating with the transistor pairs in the last 2 n-2 steps of the cascade configuration, to supply the respective control signals to those transistors of the respective differential transistor pairs that provide complete folding.
摘要翻译：交叉耦合折叠电路包括供应m个参考电压的参考电压电路，放大器电路，以响应于输入信号和参考电压和2n-I三次交叉耦合折叠电路来提供控制信号，每个其中包括三个差分晶体管对，所述差分晶体管对由所述控制信号控制，并且在所述参考电压的相应一个周围的电压范围内有效，其中m = 3（2“-1） n> - I折叠电路，在n-1个连续步骤2 ，<> 2 ，2 <°中存在差分晶体管对，为了获得完全折叠，提供开关电路，与晶体管在级联配置的最后2n-2级中对，以将相应的控制信号提供给提供完全折叠的各个差分晶体管对的晶体管。

18. 发明申请

WO02054600A9 METHOD AND APPARATUS FOR A FOLDING ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING A COURSE DECODER WITH REDUCED COMPLEXITY 审中-公开
标题翻译：用于折叠模数转换器（ADC）的方法和设备，其具有复杂度降低的套路解码器
公开(公告)号：WO02054600A9
公开(公告)日：2003-04-17
申请号：PCT/US0145417
申请日：2001-11-28
申请人： INTEL CORP
发明人： WANG DONG , GYURICS TUNDE
IPC分类号： H03M1/14 , H03M1/36
CPC分类号： H03M1/14 , H03M1/141
摘要： A method that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has a greater resolution than the course ADC. A decoder that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has greater resolution than the course ADC.
摘要翻译：将ADC模数转换器（ADC）输出值与折叠的精细ADC转换曲线斜率值相关以确定ADC电路区域的方法。折叠好的精细ADC具有比课程ADC更高的分辨率。一个解码器，用于将一个模数转换器（ADC）输出值与一个折叠的精细ADC转换曲线斜率值相关联，以确定一个ADC电路区域。折叠好的精细ADC具有比课程ADC更高的分辨率。

19. 发明申请

WO1997008834A1 FOLDING A/D CONVERTER 审中-公开
标题翻译：折叠A / D转换器
公开(公告)号：WO1997008834A1
公开(公告)日：1997-03-06
申请号：PCT/IB1996000834
申请日：1996-08-26
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , VORENKAMP, Pieter , VAN DE PLASSCHE, Rudy, Johan
IPC分类号： H03M01/36
CPC分类号： H03M1/203 , H03M1/141
摘要： In a folding A/D converter, a comparison part (CPM) provides a plurality of comparison signals Sc1...Sc9 in response to an input signal Si. The transients in the comparison signals Sc1...Sc9 are mutually shifted and substantially overlap. Because of the overlap, only a relatively small input signal variation is needed to pass all the transients. A limiting part (LIM) effectively selects portions of the transients. A combining part (CBM) effectively multiplexes these selected portions into a folding signal Sf. The selection by the limiting part (LIM) prevents distortion of the folding signal Sf, despite the overlap.
摘要翻译：在折叠A / D转换器中，比较部分（CPM）响应于输入信号Si提供多个比较信号Sc1 ... Sc9。比较信号Sc1 ... Sc9中的瞬变相互偏移并且基本上重叠。由于重叠，只需要相对较小的输入信号变化来传递所有瞬变。限制部分（LIM）有效地选择部分瞬变。组合部分（CBM）将这些选择的部分有效地多路复用成折叠信号Sf。限制部分（LIM）的选择防止折叠信号Sf的失真，尽管重叠。

20. 发明申请

WO1996002087A1 FOLDING STAGE FOR A FOLDING ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：折叠模数转换器的折叠阶段
公开(公告)号：WO1996002087A1
公开(公告)日：1996-01-25
申请号：PCT/IB1995000519
申请日：1995-06-27
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , VENES, Arnoldus, Gerardus, Wilhelmus , NAUTA, Bram
IPC分类号： H03M01/12
CPC分类号： H03M1/205 , H03M1/141
摘要： A folding stage (FB) for a folding analog-to-digital converter, the folding stage (FB) comprising: reference means having a plurality of consecutive reference terminals (RT1..RT11) for providing ascending different reference voltages; a first summing node (SNa), a second summing node (SNb) and a first output node (ONa); a plurality of differentially coupled transistor pairs (TAi/TBi), each one of the pairs comprising a first transistor (TAi) having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor (TBi) having a main current path and a control electrode which is coupled to a respective one (RTAi) of the consecutive reference terminals, the main current path of the first transistor (TAi) of consecutive transistor pairs being coupled alternately to the first summing node (SNa) and the second summing node (SNb), and the main current path of the associated second transistor (Tbi) being coupled alternately to the second summing node (SNb) and the first summing node (SNa); and a dummy structure comprising a first current source, a first dummy transistor (DTA) having a control electrode coupled to the input terminal (IT), a first main electrode connected to the first current source and a second main electrode coupled to one of the first (SNa) and second (SNb) summing nodes, a second current source, and a second dummy transistor having a control electrode coupled to a bias voltage terminal (BT), a first main electrode connected to the second current source and a second main electrode coupled to the other of the first (SNa) and second (SNb) summing nodes. The dummy structure reduces capacitive error currents in the differential output current which flows in the summing nodes of the folding stage by providing cancelling currents to the summing nodes.
摘要翻译：一种用于折叠模数转换器的折叠台（FB），所述折叠台（FB）包括：参考装置，具有用于提供上升的不同参考电压的多个连续参考端（RT1..RT11）第一求和节点（SNa），第二求和节点（SNb）和第一输出节点（ONa）; 多个差分耦合晶体管对（TAi / TBi），每对中的每一对包括具有主电流路径的第一晶体管（TAi）和耦合到输入端（IT）的控制电极，用于接收输入电压被折叠的第二晶体管（TBi）和具有主电流路径的第二晶体管（TBi）和耦合到所述连续参考端子的相应一个（RTAi）的控制电极，所述连续晶体管对的第一晶体管（TAi）的主电流路径为交替地耦合到第一求和节点（SNa）和第二求和节点（SNb），并且相关联的第二晶体管（Tbi）的主电流路径被交替地耦合到第二求和节点（SNb）和第一求和节点（SNa ）; 以及包括第一电流源，具有耦合到所述输入端（IT）的控制电极的第一虚拟晶体管（DTA））的虚拟结构，连接到所述第一电流源的第一主电极和耦合到所述第一电流源第一（SNa）和第二（SNb）求和节点，第二电流源和具有耦合到偏置电压端子（BT）的控制电极的第二虚拟晶体管，连接到第二电流源的第一主电极和第二主电极电极耦合到第一（SNa）和第二（SNb）求和节点中的另一个。虚拟结构通过向求和节点提供消除电流来减少在折叠级的求和节点中流动的差分输出电流中的电容性误差电流。

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