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1. 发明申请

WO1996002087A1 FOLDING STAGE FOR A FOLDING ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：折叠模数转换器的折叠阶段
公开(公告)号：WO1996002087A1
公开(公告)日：1996-01-25
申请号：PCT/IB1995000519
申请日：1995-06-27
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , VENES, Arnoldus, Gerardus, Wilhelmus , NAUTA, Bram
IPC分类号： H03M01/12
CPC分类号： H03M1/205 , H03M1/141
摘要： A folding stage (FB) for a folding analog-to-digital converter, the folding stage (FB) comprising: reference means having a plurality of consecutive reference terminals (RT1..RT11) for providing ascending different reference voltages; a first summing node (SNa), a second summing node (SNb) and a first output node (ONa); a plurality of differentially coupled transistor pairs (TAi/TBi), each one of the pairs comprising a first transistor (TAi) having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor (TBi) having a main current path and a control electrode which is coupled to a respective one (RTAi) of the consecutive reference terminals, the main current path of the first transistor (TAi) of consecutive transistor pairs being coupled alternately to the first summing node (SNa) and the second summing node (SNb), and the main current path of the associated second transistor (Tbi) being coupled alternately to the second summing node (SNb) and the first summing node (SNa); and a dummy structure comprising a first current source, a first dummy transistor (DTA) having a control electrode coupled to the input terminal (IT), a first main electrode connected to the first current source and a second main electrode coupled to one of the first (SNa) and second (SNb) summing nodes, a second current source, and a second dummy transistor having a control electrode coupled to a bias voltage terminal (BT), a first main electrode connected to the second current source and a second main electrode coupled to the other of the first (SNa) and second (SNb) summing nodes. The dummy structure reduces capacitive error currents in the differential output current which flows in the summing nodes of the folding stage by providing cancelling currents to the summing nodes.
摘要翻译：一种用于折叠模数转换器的折叠台（FB），所述折叠台（FB）包括：参考装置，具有用于提供上升的不同参考电压的多个连续参考端（RT1..RT11）第一求和节点（SNa），第二求和节点（SNb）和第一输出节点（ONa）; 多个差分耦合晶体管对（TAi / TBi），每对中的每一对包括具有主电流路径的第一晶体管（TAi）和耦合到输入端（IT）的控制电极，用于接收输入电压被折叠的第二晶体管（TBi）和具有主电流路径的第二晶体管（TBi）和耦合到所述连续参考端子的相应一个（RTAi）的控制电极，所述连续晶体管对的第一晶体管（TAi）的主电流路径为交替地耦合到第一求和节点（SNa）和第二求和节点（SNb），并且相关联的第二晶体管（Tbi）的主电流路径被交替地耦合到第二求和节点（SNb）和第一求和节点（SNa ）; 以及包括第一电流源，具有耦合到所述输入端（IT）的控制电极的第一虚拟晶体管（DTA））的虚拟结构，连接到所述第一电流源的第一主电极和耦合到所述第一电流源第一（SNa）和第二（SNb）求和节点，第二电流源和具有耦合到偏置电压端子（BT）的控制电极的第二虚拟晶体管，连接到第二电流源的第一主电极和第二主电极电极耦合到第一（SNa）和第二（SNb）求和节点中的另一个。虚拟结构通过向求和节点提供消除电流来减少在折叠级的求和节点中流动的差分输出电流中的电容性误差电流。

2. 发明申请

WO1997042704A3 DEGENERATED DIFFERENTIAL PAIR WITH CONTROLLABLE TRANSCONDUCTANCE 审中-公开
公开(公告)号：WO1997042704A3
公开(公告)日：1997-11-13
申请号：PCT/IB1997000483
申请日：1997-05-05
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , MENSINK, Clemens, Herman, Johan , NAUTA, Bram
IPC分类号： H03G03/30

3. 发明申请

WO1996002088A1 FOLDING STAGE AND FOLDING ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：折叠阶段和折叠模拟数字转换器
公开(公告)号：WO1996002088A1
公开(公告)日：1996-01-25
申请号：PCT/IB1995000520
申请日：1995-06-27
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , NAUTA, Bram , VENES, Arnoldus, Gerardus, Wilhelmus
IPC分类号： H03M01/12
CPC分类号： H03M1/205 , H03M1/141
摘要： A folding stage (FB) for a folding analog-to-digital converter, the folding stage (FB) comprising: reference means having a plurality of consecutive reference terminals (RT1..RT11) for providing ascending different reference voltages; a first summing node (SNa), a second summing node (SNb) and a first output node (ONa); a plurality of differentially coupled transistor pairs (TAi/TBi), each one of the pairs comprising a first transistor (TAi) having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor (TBi) having a main current path and a control electrode which is coupled to a respective one (RTi) of the consecutive reference terminals, the main current path of the first transistor (TAi) of consecutive transistor pairs being coupled alternately to the first summing node (SNa) and the second summing node (SNb), and the main current path of the associated second transistor (TBi) being coupled alternately to the second summing node (SNb) and the first summing node (SNa); and current-to-voltage converter means (IVCONV) comprising a first resistor (12) connected between the first output node (ONa) and the first summing node (SNa) to provide a first output voltage (Va) and a transconductance stage (2) having an inverting input (4) coupled to the first summing node (SNa) and an output (8) coupled to the first output node (ONa). The low input impedance of the current-to-voltage converter means (IVCONV) prevents high voltage swing at the summing nodes and reduces capacitive signal current flow. The current-to-voltage converter means (IVCONV) further provides a high output voltage swing despite of loading with a low-ohmic interpolation network.
摘要翻译：一种用于折叠模数转换器的折叠台（FB），所述折叠台（FB）包括：参考装置，具有用于提供上升的不同参考电压的多个连续参考端（RT1..RT11）第一求和节点（SNa），第二求和节点（SNb）和第一输出节点（ONa）; 多个差分耦合晶体管对（TAi / TBi），每对中的每一对包括具有主电流路径的第一晶体管（TAi）和耦合到输入端（IT）的控制电极，用于接收输入电压被折叠的第二晶体管（TBi）和具有主电流路径的第二晶体管（TBi）和耦合到连续参考端子的相应一个（RTi）的控制电极，连续晶体管对的第一晶体管（TAi）的主电流路径为交替地耦合到第一求和节点（SNa）和第二求和节点（SNb），并且相关联的第二晶体管（TBi）的主电流路径被交替地耦合到第二求和节点（SNb）和第一求和节点（SNa ）; 以及电流 - 电压转换器装置（IVCONV），包括连接在第一输出节点（ONa）和第一求和节点（SNa）之间的第一电阻器（12），以提供第一输出电压（Va）和跨导级）具有耦合到第一求和节点（SNa）的反相输入（4）和耦合到第一输出节点（ONa）的输出（8）。电流 - 电压转换器（IVCONV）的低输入阻抗防止加法节点处的高电压摆幅，并降低电容信号电流。电流 - 电压转换器（IVCONV）进一步提供高输出电压摆幅，尽管加载了低欧姆插值网络。

4. 发明申请

WO1995002931A1 LINE DRIVER WITH ADAPTIVE OUTPUT IMPEDANCE 审中-公开
标题翻译：具有自适应输出阻抗的线路驱动器
公开(公告)号：WO1995002931A1
公开(公告)日：1995-01-26
申请号：PCT/IB1994000190
申请日：1994-07-04
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , NAUTA, Bram
IPC分类号： H04B03/02
CPC分类号： H04L25/0278 , H04B3/02 , H04L25/028
摘要： A line driver comprising: an input terminal (2) for receiving an input signal, an output terminal (10) for connecting a load (8), a first (12) and a second (22) transconductance-controlled transconductor having substantially equal transconductances, each transconductor having a non-inverting input (14; 24), an inverting input (16; 26), an output (18; 28) and a common control input (20) for controlling the transconductance, the non-inverting inputs (14; 24) of the first (12) and second (22) transconductors being coupled to the input terminal (2), the outputs (18; 28) of the first (12) and second (22) transconductors being coupled to the output terminal (10), the inverting input (16) of the first transconductor (12) being coupled to a point (6) of reference potential, the inverting input (26) of the second transconductor (22) being coupled to the output terminal (10), and an amplifier (32) having a non-inverting input (34), an inverting input (36) and an output (38) coupled to, respectively, the input terminal (2), the output terminal (10) and the common control input (20) of the first (12) and the second (22) transconductors.
摘要翻译：一种线驱动器，包括：用于接收输入信号的输入端子（2），用于连接负载（8）的输出端子（10），具有基本相等的跨导的第一（12）和第二（22）跨导控制的跨导体，每个跨导体具有非反相输入（14; 24），反相输入（16; 26），输出（18; 28）和用于控制跨导的公共控制输入（20），非反相输入所述第一（12）和第二（22）跨导体耦合到所述输入端子（2），所述第一（12）和第二（22）跨导体的输出端（18; 28）端子（10），第一跨导体（12）的反相输入（16）耦合到参考电位的点（6），第二跨导体（22）的反相输入端（26）耦合到输出端子 10）和具有非反相输入（34），反相输入（36）和输出（38）的放大器（32）即，第一（12）和第二（22）跨导体的输入端子（2），输出端子（10）和公共控制输入端（20）。

5. 发明申请

WO2003065586A3 PHASE-LOCKED-LOOP WITH REDUCED CLOCK JITTER 审中-公开
公开(公告)号：WO2003065586A3
公开(公告)日：2003-08-07
申请号：PCT/IB2003/000130
申请日：2003-01-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , NAUTA, Bram , VAN DE BEEK, Remco, C., H. , VAUCHER, Cicero, S.
发明人： NAUTA, Bram , VAN DE BEEK, Remco, C., H. , VAUCHER, Cicero, S.
IPC分类号： H03L7/197
摘要： The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

6. 发明申请

WO2005091506A2 FREQUENCY DIVIDER 审中-公开
标题翻译：频率分配器
公开(公告)号：WO2005091506A2
公开(公告)日：2005-09-29
申请号：PCT/IB2005/050818
申请日：2005-03-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LEENAERTS, Dominicus, M., W. , NAUTA, Bram , ACAR, Mustafa
发明人： LEENAERTS, Dominicus, M., W. , NAUTA, Bram , ACAR, Mustafa
IPC分类号： H03K23/44

7. 发明申请

WO2006016312A1 FREQUENCY DIVIDER 审中-公开
标题翻译：频率分路器
公开(公告)号：WO2006016312A1
公开(公告)日：2006-02-16
申请号：PCT/IB2005/052534
申请日：2005-07-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ACAR, Mustafa , LEENAERTS, Dominicus, M., W. , NAUTA, Bram
发明人： ACAR, Mustafa , LEENAERTS, Dominicus, M., W. , NAUTA, Bram
IPC分类号： H03K23/54 , H03K3/356
CPC分类号： H03K23/54 , H03K3/356017 , H03K23/542
摘要： A frequency divider comprising, a first latch circuit (10) and a second latch circuit (10'), the second latch circuit (10') being crossed-coupled to the first latch circuit (10). Each latch (10; 10') comprises a respective sense amplifier coupled to a respective latch (11). The sense amplifiers comprise a first clock input for receiving a first clock signal (f, f) and 5 respective complementary first clock signal having a first frequency. The latches (11) comprise a second clock input (2f; 2f) for receiving a second clock signal and respective complementary second clock signal having a second frequency, the second frequency being substantially double the first frequency.
摘要翻译：一种分频器，包括第一锁存电路（10）和第二锁存电路（10'），第二锁存电路（10'）与第一锁存电路（10）交叉耦合。每个锁存器（10; 10'）包括耦合到相应的锁存器（11）的相应的读出放大器。感测放大器包括用于接收具有第一频率的第一时钟信号（f，f）和相应的互补第一时钟信号的第一时钟输入。锁存器（11）包括用于接收第二时钟信号的第二时钟输入端（2f; 2f）和具有第二频率的相应的互补第二时钟信号，第二频率基本上是第一频率的两倍。

8. 发明申请

WO2004021574A1 PHASE LOCKED LOOP 审中-公开
标题翻译：相位锁定环
公开(公告)号：WO2004021574A1
公开(公告)日：2004-03-11
申请号：PCT/IB2003/003726
申请日：2003-07-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DE BEEK, Remco, C., H. , KLUMPERINK, Eric, A., M. , NAUTA, Bram , VAUCHER, Cicero, S.
发明人： VAN DE BEEK, Remco, C., H. , KLUMPERINK, Eric, A., M. , NAUTA, Bram , VAUCHER, Cicero, S.
IPC分类号： H03L7/089
CPC分类号： H03L7/191 , H03D13/00 , H03L7/087 , H03L7/089 , H03L7/0893 , H03L7/113
摘要： A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).
摘要翻译：一种锁相环，包括用于确定参考信号（Ref）和相互相移信号（I，Q）之间的相位差的相位检测器（100），以产生频率控制信号（U，D），相位检测器（100）包括：用于通过参考信号（Ref）和相对相移信号（I，Q）之一的二进制相乘来获得所述频率控制信号（U，D）中的第一个的装置（10）。以及用于通过相对相移信号（I，Q）的二进制相乘来获得所述频率控制信号（U，D）中的第二个的装置（20）。

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