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1. 发明申请

WO2002065643A2 CAPACITIVE FOLDING CIRCUIT FOR USE IN A FOLDING/INTERPOLATING ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：用于折叠/插值模拟数字转换器的电容折叠电路
公开(公告)号：WO2002065643A2
公开(公告)日：2002-08-22
申请号：PCT/US2002/003878
申请日：2002-02-11
申请人： BROADCOM CORPORATION
发明人： BULT, Klaas
IPC分类号： H03M1/00
CPC分类号： H03M1/205 , H03M1/141
摘要： An M-bit folding/interpolating analog-to-digital converter (ADC) circuit, comprising a reference voltage generator, a converter, an interpolator, an amplifying stage, a comparator, and an encoder. The converter has an amplifier that receives at least one of a plurality of first reference voltage signals and outputs a plurality of coarse bits. The converter also has N-number of folding blocks, which output a plurality of folded signals. Each folding block comprises a plurality of capacitors, a differential amplifier and a feedback element. The folded signals output by the converter are then interpolated, amplified, compared and output as a plurality of fine bits. The encoder receives the coarse and fine bits and outputs the digital signal.
摘要翻译：一种M位折叠/内插模数转换器（ADC）电路，包括参考电压发生器，转换器，内插器，放大级，比较器和编码器。转换器具有放大器，其接收多个第一参考电压信号中的至少一个并输出多个粗位。转换器还具有N个折叠块，其输出多个折叠信号。每个折叠块包括多个电容器，差分放大器和反馈元件。然后，由转换器输出的折叠信号被内插，放大，比较和输出为多个精细位。编码器接收粗细位并输出数字信号。

2. 发明申请

WO2008029778A1 フォールディング回路およびアナログ－デジタル変換器审中-公开
标题翻译：折叠电路和模拟数字转换器
公开(公告)号：WO2008029778A1
公开(公告)日：2008-03-13
申请号：PCT/JP2007/067161
申请日：2007-09-04
申请人：ソニー株式会社 , 大川剛史 , 尾野孝一 , 松浦浩二 , 山下幸利 , 豊村純次 , 中村章吾 , 金川典史
发明人：大川剛史 , 尾野孝一 , 松浦浩二 , 山下幸利 , 豊村純次 , 中村章吾 , 金川典史
IPC分类号： H03M1/36 , H03M1/14
CPC分类号： H03M1/0863 , H03M1/0682 , H03M1/141 , H03M1/205 , H03M1/365
摘要：　小信号応答性がよく、クロック信号の負荷を軽減でき、面積の増大を防止することができるフォールディング回路およびアナログ－デジタル変換器を提供する。複数の異なる電圧を基準電圧として発生させる基準電圧発生回路と、複数の基準電圧とアナログ入力電圧との差電圧を差電流に変換して出力する複数の増幅回路と、を有し、増幅回路の出力端がそれぞれ交互に接続され、増幅回路はカスコード出力トランジスタ（１４５，１４６）を有する差動増幅回路で構成されており、カスコード出力トランジスタ（１４５，１４６）の両ソース間に制御クロックに同期してオン状態となるスイッチ（１４４）が設けられている。
摘要翻译：折叠电路和模数转换器，其中对小信号的响应得到改善，可以减少对时钟信号的负载，并且可以防止电路面积的增加。包括产生多个不同电压作为参考电压的参考电压产生电路; 以及多个放大电路，其将多个参考电压之间的差分电压和模拟输入电压转换为差分电流并输出这些差分电流。放大电路的输出端子交替连接。每个放大电路包括具有共源共栅输出晶体管（145,146）的差分放大器电路。与控制时钟同步地导通的开关（144）连接在共源共栅输出晶体管（145,146）的源极之间。

3. 发明申请

WO1996002088A1 FOLDING STAGE AND FOLDING ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：折叠阶段和折叠模拟数字转换器
公开(公告)号：WO1996002088A1
公开(公告)日：1996-01-25
申请号：PCT/IB1995000520
申请日：1995-06-27
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , NAUTA, Bram , VENES, Arnoldus, Gerardus, Wilhelmus
IPC分类号： H03M01/12
CPC分类号： H03M1/205 , H03M1/141
摘要： A folding stage (FB) for a folding analog-to-digital converter, the folding stage (FB) comprising: reference means having a plurality of consecutive reference terminals (RT1..RT11) for providing ascending different reference voltages; a first summing node (SNa), a second summing node (SNb) and a first output node (ONa); a plurality of differentially coupled transistor pairs (TAi/TBi), each one of the pairs comprising a first transistor (TAi) having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor (TBi) having a main current path and a control electrode which is coupled to a respective one (RTi) of the consecutive reference terminals, the main current path of the first transistor (TAi) of consecutive transistor pairs being coupled alternately to the first summing node (SNa) and the second summing node (SNb), and the main current path of the associated second transistor (TBi) being coupled alternately to the second summing node (SNb) and the first summing node (SNa); and current-to-voltage converter means (IVCONV) comprising a first resistor (12) connected between the first output node (ONa) and the first summing node (SNa) to provide a first output voltage (Va) and a transconductance stage (2) having an inverting input (4) coupled to the first summing node (SNa) and an output (8) coupled to the first output node (ONa). The low input impedance of the current-to-voltage converter means (IVCONV) prevents high voltage swing at the summing nodes and reduces capacitive signal current flow. The current-to-voltage converter means (IVCONV) further provides a high output voltage swing despite of loading with a low-ohmic interpolation network.
摘要翻译：一种用于折叠模数转换器的折叠台（FB），所述折叠台（FB）包括：参考装置，具有用于提供上升的不同参考电压的多个连续参考端（RT1..RT11）第一求和节点（SNa），第二求和节点（SNb）和第一输出节点（ONa）; 多个差分耦合晶体管对（TAi / TBi），每对中的每一对包括具有主电流路径的第一晶体管（TAi）和耦合到输入端（IT）的控制电极，用于接收输入电压被折叠的第二晶体管（TBi）和具有主电流路径的第二晶体管（TBi）和耦合到连续参考端子的相应一个（RTi）的控制电极，连续晶体管对的第一晶体管（TAi）的主电流路径为交替地耦合到第一求和节点（SNa）和第二求和节点（SNb），并且相关联的第二晶体管（TBi）的主电流路径被交替地耦合到第二求和节点（SNb）和第一求和节点（SNa ）; 以及电流 - 电压转换器装置（IVCONV），包括连接在第一输出节点（ONa）和第一求和节点（SNa）之间的第一电阻器（12），以提供第一输出电压（Va）和跨导级）具有耦合到第一求和节点（SNa）的反相输入（4）和耦合到第一输出节点（ONa）的输出（8）。电流 - 电压转换器（IVCONV）的低输入阻抗防止加法节点处的高电压摆幅，并降低电容信号电流。电流 - 电压转换器（IVCONV）进一步提供高输出电压摆幅，尽管加载了低欧姆插值网络。

4. 发明申请

WO02054600A3 METHOD AND APPARATUS FOR A FOLDING ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING A COURSE DECODER WITH REDUCED COMPLEXITY 审中-公开
标题翻译：具有降低复杂度的游戏解码器的折叠模数转换器（ADC）的方法和装置
公开(公告)号：WO02054600A3
公开(公告)日：2003-07-24
申请号：PCT/US0145417
申请日：2001-11-28
申请人： INTEL CORP
发明人： WANG DONG , GYURICS TUNDE
IPC分类号： H03M1/14 , H03M1/36
CPC分类号： H03M1/14 , H03M1/141
摘要： A method that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has a greater resolution than the course ADC. A decoder that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has greater resolution than the course ADC.
摘要翻译：一种将课程模数转换器（ADC）输出值与折叠的精细ADC转换曲线斜率值相关联的方法，以确定ADC电路区域。折叠的精细ADC具有比当前ADC更高的分辨率。一个解码器，将一个课程模数转换器（ADC）的输出值与折叠的精细ADC转换曲线斜率值相关联，以确定ADC电路区域。折叠的精细ADC具有比当前ADC更高的分辨率。

5. 发明申请

WO0158010A3 DEVICES AND METHODS FOR CALIBRATING AMPLIFIER STAGES AND FOR COMPENSATING FOR ERRORS IN AMPLIFIER STAGES OF SERIES-CONNECTED COMPONENTS 审中-公开
标题翻译：用于校准的放大器级和放大器定位误差补偿装置和方法中的阶段的上游部件
公开(公告)号：WO0158010A3
公开(公告)日：2002-12-27
申请号：PCT/DE0100238
申请日：2001-01-19
申请人： INFINEON TECHNOLOGIES AG , ENGL BERNHARD
发明人： ENGL BERNHARD
IPC分类号： G11C27/02 , H03F3/45 , H03M1/10 , H03M1/36 , H03M1/06
CPC分类号： H03M1/1014 , G11C27/026 , H03F3/45753 , H03F3/45771 , H03F2200/331 , H03F2203/45048 , H03M1/141
摘要： The inventive amplifier stage calibration comprises the following steps: creating conditions that are suitable for calibrating the amplifier stage; comparing signals output by the amplifier stage or comparing electrical quantities occurring inside the amplifier stage with one another or with assigned reference values, and; modifying the attributes of the amplifier stage based on the result of the comparison. The described compensation of errors in amplifier stages of series-connected components is effected by correspondingly calibrating the amplifier stage. The inventive devices and methods enable the calibration of amplifier stages and the compensation for errors in amplifier stages of series-connected components to be carried out rapidly and precisely in an astonishingly simple manner.
摘要翻译：所描述的放大器级校准包括以下步骤：为所述放大器级的条件的校准创建权宜之计，比较所述放大器级的信号的输出或与彼此或与相关联的基准值的放大器级的电气量内发生，并且改变所述放大器级的要被校准特性的函数该比较的结果。为在放大器的误差补偿级描述通过放大器级的适当的校准发生上游部件。所描述的装置和方法描述了放大器级的校准和在放大器级中的错误一个非常简单的方式上游部件被快速，准确地进行补偿。

6. 发明申请

WO02054600A2 METHOD AND APPARATUS FOR A FOLDING ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING A COURSE DECODER WITH REDUCED COMPLEXITY 审中-公开
标题翻译：具有降低复杂度的游戏解码器的折叠模数转换器（ADC）的方法和装置
公开(公告)号：WO02054600A2
公开(公告)日：2002-07-11
申请号：PCT/US2001/045417
申请日：2001-11-28
IPC分类号： H03M1/14 , H03M1/36
CPC分类号： H03M1/14 , H03M1/141
摘要： A method that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has a greater resolution than the course ADC. A decoder that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has greater resolution than the course ADC.
摘要翻译：一种将课程模数转换器（ADC）输出值与折叠的精细ADC转换曲线斜率值相关联的方法，以确定ADC电路区域。折叠的精细ADC具有比当前ADC更高的分辨率。一个解码器，将一个课程模数转换器（ADC）的输出值与折叠的精细ADC转换曲线斜率值相关联，以确定ADC电路区域。折叠的精细ADC具有比当前ADC更高的分辨率。

7. 发明申请

WO01058010A2 DEVICES AND METHODS FOR CALIBRATING AMPLIFIER STAGES AND FOR COMPENSATING FOR ERRORS IN AMPLIFIER STAGES OF SERIES-CONNECTED COMPONENTS 审中-公开
标题翻译：用于校准的放大器级和放大器定位误差补偿装置和方法中的阶段的上游部件
公开(公告)号：WO01058010A2
公开(公告)日：2001-08-09
申请号：PCT/DE2001/000238
申请日：2001-01-19
IPC分类号： G11C27/02 , H03F3/45 , H03M1/10 , H03M1/36 , H03F1/00
CPC分类号： H03M1/1014 , G11C27/026 , H03F3/45753 , H03F3/45771 , H03F2200/331 , H03F2203/45048 , H03M1/141
摘要： The inventive amplifier stage calibration comprises the following steps: creating conditions that are suitable for calibrating the amplifier stage; comparing signals output by the amplifier stage or comparing electrical quantities occurring inside the amplifier stage with one another or with assigned reference values, and; modifying the attributes of the amplifier stage based on the result of the comparison. The described compensation of errors in amplifier stages of series-connected components is effected by correspondingly calibrating the amplifier stage. The inventive devices and methods enable the calibration of amplifier stages and the compensation for errors in amplifier stages of series-connected components to be carried out rapidly and precisely in an astonishingly simple manner.
摘要翻译：所描述的放大器级校准包括以下步骤：为所述放大器级的条件的校准创建权宜之计，比较所述放大器级的信号的输出或与彼此或与相关联的基准值的放大器级的电气量内发生，并且改变所述放大器级的要被校准特性的函数该比较的结果。为在放大器的误差补偿级描述通过放大器级的适当的校准发生上游部件。所描述的装置和方法描述了放大器级的校准和在放大器级中的错误一个非常简单的方式上游部件被快速，准确地进行补偿。

8. 发明申请

WO9709788A3 A/D CONVERSION WITH FOLDING AND INTERPOLATION 审中-公开
标题翻译： A / D转换与折叠和插值
公开(公告)号：WO9709788A3
公开(公告)日：1997-04-03
申请号：PCT/IB9600869
申请日：1996-08-29
申请人： PHILIPS ELECTRONICS NV , PHILIPS NORDEN AB
发明人： VORENKAMP PIETER , VENES ARNOLDUS GERARDUS WILHEL , VAN DE PLASSCHE RUDY JOHAN
IPC分类号： H03M1/34 , H03M1/20 , H03M1/36
CPC分类号： H03M1/204 , H03M1/141
摘要： An A/D converter has an input part IS which provides transitions T1..Tx associated with different levels of an analog input signal Vin. An intermediate part IMS carries out folding and interpolation operations F1, I1 and F2, I2..IN on the transitions T1..Tx to obtain a set of bit-determining signals XO.. XQ. At least one of the operations, folding F1, F2,.. or interpolation I1, IN, is carried out more than once in alternation with the other operation, interpolation I1, IN or folding F1, F2,.. respectively. An output part OS provides a digital output signal Do on the basis of the bit-determining signals XO..XQ. Such an A/D converter can be implemented in a cost-efficient manner and may be combined with digital signal-processing circuitry.

9. 发明申请

WO2010033232A2 UNIFIED ARCHITECTURE FOR FOLDING ADC 审中-公开
公开(公告)号：WO2010033232A2
公开(公告)日：2010-03-25
申请号：PCT/US2009005225
申请日：2009-09-18
申请人： NAT SEMICONDUCTOR CORP , TAFT ROBERT CALLAGHAN
发明人： TAFT ROBERT CALLAGHAN
IPC分类号： H03M1/12
CPC分类号： H03M1/141
摘要： A system, apparatus and method for a folding analog-to-digital converter (ADC) are described. The general architecture of the folding ADC includes an array (1 - N) of cascaded folding amplifier stages, a distributed array of fine comparators, and an encoder. Each folding amplifier stage includes folding amplifiers that are configured to receive inputs from a prior stage, and also generate output signals for the next stage. The folding amplifiers output signals for a given stage are evaluated by a corresponding comparator stage, which may include multiple comparators, and also optionally coupled to an interpolator. The outputs of the comparators from all stages are collectively evaluated by the encoder, which generates the output of the folding ADC. Unlike conventional folding ADCs that require fine and coarse channels, the presently described folding ADC provides conversion without the need for a coarse channel. The encoder can also be arranged to facilitate recursive error correction.

10. 发明申请

WO2006053840A1 CONVERTISSEUR ANALOGIQUE-NUMERIQUE 审中-公开
标题翻译：模拟/数字转换器
公开(公告)号：WO2006053840A1
公开(公告)日：2006-05-26
申请号：PCT/EP2005/055774
申请日：2005-11-07
申请人： ATMEL GRENOBLE , MORISSON, Richard
发明人： MORISSON, Richard
IPC分类号： H03M1/06
CPC分类号： H03M1/203 , H03M1/141
摘要： L'invention concerne les convertisseurs analogiques numériques (CAN) dont l'architecture comprend des circuits de repliement en cascade, amont (CRAM) et aval (CRAV) avec un circuit d'interpolation (CI) interposé entre les deux circuits de repliement. Pour éviter des erreurs de conversion dues à la présence du circuit d'interpolation, on interpose en aval du circuit d'interpolation un étage de compensation de gain (ATT) qui agit sur certaines des sorties du circuit d'interpolation pour ramener à la même pente de variation (en fonction de la tension d'entrée Vin à convertir) tous les signaux qui sortent du circuit d'interpolation, avant de les appliquer au circuit de repliement aval. Le circuit de compensation de gain est de préférence un simple atténuateur à réseau de résistances.
摘要翻译：本发明涉及具有包括上游（CRAM）和下游（CRAV）级联折叠电路的架构的模拟/数字转换器（ADC），其中插入电路（CI）设置在所述两个折叠电路之间。为了防止由于内插电路的存在而产生的转换误差，增益补偿级（ATT）被布置在所述内插电路的下游，其作用于内插电路的一些输出，以确保所有信号在将电路施加到下游折叠电路之前，使电路具有相同的变化斜率（作为要转换的输入电压Vin的函数）。增益补偿电路优选地包括具有电阻网络的简单衰减器。

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