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11. 发明申请

WO2004038802A2 INTEGRIERTE SCHALTUNGSANORDNUNG MIT KONDENSATOREN UND MIT VORZUGSWEISE PLANAREN TRANSISTOREN UND HERSTELLUNGSVERFAHREN 审中-公开
标题翻译：与电容和优选具有平面晶体管和方法集成电路
公开(公告)号：WO2004038802A2
公开(公告)日：2004-05-06
申请号：PCT/DE2003/003354
申请日：2003-10-10
申请人： INFINEON TECHNOLOGIES AG , BREDERLOW, Ralf , HARTWICH, Jessica , PACHA, Christian , RÖSNER, Wolfgang , SCHULZ, Thomas
发明人： BREDERLOW, Ralf , HARTWICH, Jessica , PACHA, Christian , RÖSNER, Wolfgang , SCHULZ, Thomas
IPC分类号： H01L27/12
CPC分类号： H01L27/1085 , H01L21/84 , H01L27/10805 , H01L27/1203
摘要： Erläutert wird unter anderem eine integrierte Schaltungsanordnung (140), die einen vorzugsweise planaren Transistor (142) und einen Kondensator (144) enthält. Die untere Elektrode des Kondensators (144) ist gemeinsam mit einem Kanalbereich des Transistors (142) in einem SOI-Substrat angeordnet. Die Schaltungsanordnung (140) ist einfach herzustellen und hat hervorragende elektronische Eigenschaften.
摘要翻译：进行了说明，除其他外，其包含优选的平面型晶体管（142）和电容器（144）的集成电路装置（140）。电容器（144）的下部电极与在SOI衬底的晶体管（142）的沟道区布置在一起。所述电路（140）是易产生并具有优异的电子性质。

12. 发明申请

WO00002249A2 INTEGRATED CIRCUIT, METHOD FOR PRODUCING THE SAME AND WAFER WITH A NUMBER OF INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路方法及其与晶圆随着集成电路中的几个
公开(公告)号：WO00002249A2
公开(公告)日：2000-01-13
申请号：PCT/DE1999/001934
申请日：1999-07-01
IPC分类号： H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/04
CPC分类号： H01L27/10844 , H01L27/10805 , H01L29/045
摘要： The inventive integrated circuit comprises at least one first component with a structure to which defects may be adjacent and a second component with at least one p-n junction (Ü'), said components being situated next to each other in a substrate (1) whose defects extend in a defect plane (d) at least in sections. The crystal orientation of the substrate (1) in relation to the first component and the second component is chosen with the aim of keeping the defects on the surfaces without them intersecting the p-n junction (Ü'), in order to prevent undesirable leakage currents through the p-n junction (Ü'). The integrated circuit is especially a DRAM cell arrangement with extended retention time. The inventive integrated circuit is produced by mounting photo-resist masks of a known layout on the starting wafer, the masks being rotated in relation to a known starting wafer. Alternatively, photo-resist masks of a known layout can be mounted on a starting wafer in a conventional manner, the output wafer having a marking showing the course of the defect plane (d).
摘要翻译：所述集成电路装置包括至少在一个基片具有可以在邻近缺陷彼此相邻的结构，并且具有至少一个pn结（B“）的第二组分的第一组分（1）被布置，其至少缺陷部分中缺陷电平（d）延伸。被选择的衬底（1）相对于所述第一组分和所述第二组分的晶体取向，使得缺陷被记录在表面上而不被切断p-n结。以这种方式，能够避免通过p-n结（B“）不希望的泄漏。集成电路装置是特别具有增加的保留时间的DRAM单元的布置。为了制备集成电路装置光刻胶掩模可以被安装在一个已知的晶片布局相对于扭转的已知的起始晶片的输出。可替代地，光致抗蚀剂掩模的已知布局可以在输出晶片上以常规方式应用，但起始晶片具有示出的缺陷电平（d）的过程中的标签。

13. 发明申请

WO1994010704A1 INTEGRATED CIRCUIT WITH LAYERED SUPERLATTICE MATERIAL AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有层状超导材料的集成电路及其制造方法
公开(公告)号：WO1994010704A1
公开(公告)日：1994-05-11
申请号：PCT/US1993010127
申请日：1993-10-21
申请人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD.
发明人： SYMETRIX CORPORATION , OLYMPUS OPTICAL CO., LTD. , YOSHIMORI, Hiroyuki , WATANABE, Hitoshi , PAZ DE ARUAJO, Carlos, A. , HIRAIDE, Shuzo , McMILLAN, Larry, D. , MIHARA, Takashi
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , C23C16/45561 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/31691 , H01L27/10805 , H01L28/55 , H01L28/56 , H01L28/60
摘要： A method of fabricating a layered superlattice DRAM (100) compatible with conventional silicon CMOS technology. A MOSFET (72) is formed on a silicon substrate (71). A thick layer (77D) of BPSG followed by a thin SOG layer (77E) overlies the MOSFET (72). A capacitor (80) is formed by depositing a layer (81) of platinum, annealing, depositing an intermediate layer (84) comprising a layered superlattice material, annealing, depositing a second layer (84) of platinum, then patterning the capacitor (80). Another SOG layer (86) is deposited, contact holes (106, 107) to the MOSFET (72) and capacitor (80) are partially opened, the SOG (86) is annealed, the contact holes (106, 107) are completely opened, and a Pt/Ti/PtSi wiring layer (88, 288) is deposited.
摘要翻译：一种制造与常规硅CMOS技术兼容的分层超晶格DRAM（100）的方法。在硅衬底（71）上形成MOSFET（72）。 BPSG的厚层（77D）之后是薄的SOG层（77E）覆盖在MOSFET（72）上。通过沉积铂的层（81），退火，沉积包括层状超晶格材料的中间层（84），退火，沉积铂的第二层（84），然后对电容器（80）进行构图，形成电容器（80））。沉积另一个SOG层（86），接触孔（106,107）到MOSFET（72）和电容器（80）被部分打开，SOG（86）退火，接触孔（106,107）被完全打开，并沉积Pt / Ti / PtSi布线层（88,288）。

14. 发明申请

WO1992012539A1 SEMICONDUCTOR MEMORY OF DYNAMIC TYPE 审中-公开
标题翻译：动态类型的半导体记忆
公开(公告)号：WO1992012539A1
公开(公告)日：1992-07-23
申请号：PCT/JP1991001800
申请日：1991-12-27
申请人： OHMI, Tadahiro
IPC分类号： H01L27/10
CPC分类号： H01L27/10805
摘要： A memory cell of a DRAM which can be easily manufactured, and has a high breakdown voltage, and a large capacitance. The semiconductor memory of a dynamic type has capacitors for accumulating signal charges, each capacitor comprising two electrodes having nearly equal areas and facing each other with a first insulator interposed between, and a second insulator adjoining to the electrodes. The dielectric constant of the first insulator is larger than that of the second insulator.
摘要翻译：可以容易地制造并具有高击穿电压和大电容的DRAM的存储单元。动态类型的半导体存储器具有用于累积信号电荷的电容器，每个电容器包括具有几乎相等面积的两个电极，并且彼此面对，并且第一绝缘体插入在与电极相邻的第二绝缘体之间。第一绝缘体的介电常数大于第二绝缘体的介电常数。

15. 发明申请

WO2016174546A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2016174546A1
公开(公告)日：2016-11-03
申请号：PCT/IB2016/052227
申请日：2016-04-20
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： TEZUKA, Sachiaki , TANAKA, Tetsuhiro , ENDO, Toshiya , ICHIJO, Mitsuhiro
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/08 , H01L27/088 , H01L27/108 , H01L27/146 , H01L29/786 , H01L51/50 , H05B33/14
CPC分类号： H01L29/7869 , H01L21/8258 , H01L27/0688 , H01L27/10805 , H01L27/10873 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/127 , H01L29/66969 , H01L29/7855 , H01L29/78603 , H01L29/78648
摘要： A semiconductor device includes a semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator. The first conductor and the semiconductor partly overlap with each other with the first insulator positioned therebetween. The second conductor and the third conductor have regions in contact with the semiconductor. The semiconductor has a region in contact with the second insulator. The fourth insulator has a first region and a second region. The first region is thicker than the second region. The first region has a region in contact with the second insulator. The second region has a region in contact with the third insulator. The fourth conductor and the second insulator partly overlap with each other with the fourth insulator positioned therebetween.
摘要翻译：半导体器件包括半导体，第一导体，第二导体，第三导体，第四导体，第一绝缘体，第二绝缘体，第三绝缘体和第四绝缘体。第一导体和半导体部分地彼此重叠，第一绝缘体位于它们之间。第二导体和第三导体具有与半导体接触的区域。半导体具有与第二绝缘体接触的区域。第四绝缘体具有第一区域和第二区域。第一区域比第二区域厚。第一区域具有与第二绝缘体接触的区域。第二区域具有与第三绝缘体接触的区域。第四导体和第二绝缘体彼此部分重叠，第四绝缘体位于它们之间。

16. 发明申请

WO2014119596A1 半導体装置およびその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2014119596A1
公开(公告)日：2014-08-07
申请号：PCT/JP2014/051903
申请日：2014-01-29
申请人：ピーエスフォールクスコエスエイアールエル , 迫川泰幸
发明人：迫川　泰幸
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/7831 , H01L21/28044 , H01L21/28114 , H01L21/28247 , H01L27/0207 , H01L27/10805 , H01L27/10873 , H01L27/10894 , H01L29/42376 , H01L29/4925 , H01L29/517 , H01L29/66409 , H01L29/6656 , H01L29/6659
摘要：　高誘電率絶縁材料を含み第１の幅を有するゲート絶縁膜と、第１の幅より狭い第２の幅を有する下部ゲート電極と、第３の幅を有する上部ゲート電極と、上部ゲート電極の側部と上部ゲート電極の下部の一部と下部ゲート電極の一部と下部ゲート電極と接しないゲート絶縁膜の上面の一部とゲート絶縁膜の側面を覆う第１のスペーサ層と、を備える半導体装置。
摘要翻译：一种半导体器件，其具有：具有高介电常数绝缘材料并具有第一宽度的栅极绝缘膜; 下栅电极，其具有比所述第一宽度窄的第二宽度; 具有第三宽度的上栅电极; 以及第一间隔层，其覆盖上栅电极的侧部，上栅电极的下部的一部分，下栅电极的一部分，栅极绝缘膜的上表面的一部分，所述部分上表面与下栅极电极以及栅绝缘膜的侧表面不接触。

17. 发明申请

WO2013184308A1 DRAM WITH A NANOWIRE ACCESS TRANSISTOR 审中-公开
标题翻译：具有纳米访问晶体管的DRAM
公开(公告)号：WO2013184308A1
公开(公告)日：2013-12-12
申请号：PCT/US2013/041038
申请日：2013-05-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： CHANG, Josephine , SLEIGHT, Jeffrey, W.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10805 , B82Y10/00 , H01L21/84 , H01L27/0207 , H01L27/10873 , H01L27/1203 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/945 , Y10S977/89 , Y10S977/943
摘要： A semiconductor nanowire is formed integrally with a wraparound semiconductor portion (30D) that contacts sidewalls of a conductive cap structure (18) located at an upper portion of a deep trench and contacting an inner electrode (16) of a deep trench capacitor. The semiconductor nanowire (30N) is suspended from above a buried insulator layer (20). A gate dielectric layer (32L) is formed on the surfaces of the semiconductor material structure (30P) including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion (30D) is formed around a center portion of the semiconductor nanowire and gate spacers (52) are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
摘要翻译：半导体纳米线与环绕半导体部分（30D）一体地形成，该环绕半导体部分（30D）接触位于深沟槽的上部并且与深沟槽电容器的内部电极（16）接触的导电盖结构（18）的侧壁。半导体纳米线（30N）从掩埋绝缘体层（20）的上方悬挂。在包括半导体纳米线和环绕半导体部分的半导体材料结构（30P）的表面上形成栅极电介质层（32L）。围绕半导体纳米线的中心部分形成环形栅电极部分（30D），形成栅极间隔物（52）。去除图案化的半导体材料结构的物理曝光部分，并且执行选择性外延和金属化以将半导体纳米线的源极端部连接到导电帽结构。

18. 发明申请

WO2011086847A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2011086847A1
公开(公告)日：2011-07-21
申请号：PCT/JP2010/073643
申请日：2010-12-20
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , YAMAZAKI, Shunpei , KOYAMA, Jun , KATO, Kiyoshi
发明人： YAMAZAKI, Shunpei , KOYAMA, Jun , KATO, Kiyoshi
IPC分类号： H01L27/105 , C23C14/08 , H01L21/8234 , H01L21/8242 , H01L21/8247 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/115 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10805 , G11C5/063 , G11C11/403 , G11C11/405 , G11C16/02 , H01L27/11521 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L28/60
摘要： An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line, a second signal line, a word line, and a memory cell connected between the source-bit lines. The memory cell includes a first transistor, a second transistor, and a capacitor. The second transistor is formed including an oxide semiconductor material. A gate electrode of the first transistor, one of a source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another. The source-bit line and a source electrode of the first transistor are electrically connected to each other. Another source-bit line adjacent to the above source-bit line and a drain electrode of the first transistor are electrically connected to each other.
摘要翻译：目的是提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入操作的次数没有限制。半导体器件包括源极线，第一信号线，第二信号线，字线和连接在源极线之间的存储单元。存储单元包括第一晶体管，第二晶体管和电容器。形成包括氧化物半导体材料的第二晶体管。第一晶体管的栅极，源极和漏极之一以及电容器的电极中的一个彼此电连接。第一晶体管的源极线和源电极彼此电连接。与上述源极线相邻的另一个源极线和第一晶体管的漏极彼此电连接。

19. 发明申请

WO2008140876A1 MEMORY ARRAYS, SEMICONDUCTOR CONSTRUCTIONS AND ELECTRONIC SYSTEMS; AND METHODS OF FORMING MEMORY ARRAYS, SEMICONDUCTOR CONSTRUCTIONS AND ELECTRONIC SYSTEMS 审中-公开
标题翻译：记忆阵列，半导体结构和电子系统; 和形成记忆阵列，半导体结构和电子系统的方法
公开(公告)号：WO2008140876A1
公开(公告)日：2008-11-20
申请号：PCT/US2008/059788
申请日：2008-04-09
申请人： MICRON TECHNOLOGY, INC.
发明人： PAREKH, Kunal, R.
IPC分类号： H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/78 , H01L21/762
CPC分类号： H01L29/78 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/10873 , H01L27/1207 , H01L29/0603 , H01L29/7841
摘要： The present invention, relates to semiconductor constructions over partial SOI substrate, and manufacturing methods therefor. Some embodiments include DRAM (10) having transistor gates (54) extending partially over SOI (19), and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals (18), and in some embodiments the unit cells may comprise capacitors having storage nodes (106, 108, 110, 112) in direct contact with sidewalls of the active region pedestals. Some embodiments include OC1 T memory having transistor gates entirely over SOI, and methods of forming such OC1 T memory.
摘要翻译：本发明涉及部分SOI衬底上的半导体结构及其制造方法。一些实施例包括具有在SOI（19）上部分延伸的晶体管栅极（54）的DRAM（10）以及形成这种DRAM的方法。 DRAM的单位单元可以在有源区域基座（18）内，并且在一些实施例中，单位单元可以包括具有与有源区域基座的侧壁直接接触的存储节点（106,108,110,112）的电容器。一些实施例包括具有完全在SOI上的晶体管栅极的OC1T存储器，以及形成这种OC1T存储器的方法。

20. 发明申请

WO2008073776A2 TRANSISTOR GATES INCLUDING COBALT SILICIDE, SEMICONDUCTOR DEVICE STRUCTURES INCLUDING THE TRANSISTOR GATES, PRECURSOR STRUCTURES, AND METHODS OF FABRICATION 审中-公开
标题翻译：包括硅化钴的晶体管栅极，包括晶体管栅极的半导体器件结构，前驱体结构和制造方法
公开(公告)号：WO2008073776A2
公开(公告)日：2008-06-19
申请号：PCT/US2007086487
申请日：2007-12-05
申请人： MICRON TECHNOLOGY INC , HU YONGJUN JEFF
发明人： HU YONGJUN JEFF
IPC分类号： H01L21/28
CPC分类号： H01L29/4975 , H01L21/28273 , H01L27/105 , H01L27/10805 , H01L27/10891 , H01L27/115 , H01L27/11521
摘要： A method for fabricating a transistor gate with a conductive element that includes cobalt suicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In addition, semiconductor devices (e.g., DRAM devices and NAND flash memory devices) with transistor gates that include cobalt suicide in their conductive elements are also disclosed, as are transistors with raised source and drain regions and cobalt suicide in the transistor gates thereof. Intermediate semiconductor device structures that include transistor gates with sacrificial material or a gap between upper portions of sidewall spacers are also disclosed.
摘要翻译：一种制造具有包括硅化钴的导电元件的晶体管栅极的方法包括使用牺牲材料作为晶体管栅极的侧壁间隔物之间的放置保持器，直到高温工艺（例如制造凸起的源极和漏极区域）之后，已经完成。此外，还公开了在其导电元件中包含硅化钴的晶体管栅极的半导体器件（例如，DRAM器件和NAND闪存器件），以及在其晶体管栅极中具有升高的源极和漏极区以及钴硅化物的晶体管。还公开了包括具有牺牲材料的晶体管栅极或侧壁间隔物的上部之间的间隙的中间半导体器件结构。

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