专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

WO2003017357A1 PROCEDE D'OBTENTION D'UNE COUCHE MINCE SEMICONDUCTRICE AUTO-PORTEE POUR CIRCUITS ELECTRONIQUES 审中-公开
标题翻译：用于获得电子电路的自载体半导体薄层的方法
公开(公告)号：WO2003017357A1
公开(公告)日：2003-02-27
申请号：PCT/FR2002/002879
申请日：2002-08-14
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , RAYSSAC, Olivier , MAZURE, Carlos , GHYSELEN, Bruno
发明人： RAYSSAC, Olivier , MAZURE, Carlos , GHYSELEN, Bruno
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： L'invention concerne un procédé d'obtention d'une couche mince auto-portée d'un matériau semi-conducteur, supportant au moins un composant et/ou circuit électronique (3) sur une de ses faces, à partir d'une plaquette (1) dudit matériau, celle-ci présentant une face avant (2), supportant ou destinée à supporter au moins un composant et/ou circuit électronique (3) et une face arrière (4'). Ce procédé est remarquable en ce qu'il comprend les étapes consistant à : a) implanter des espèces atomiques à l'intérieur de ladite plaquette (1), depuis sa face arrière (4, 4'), de façon à obtenir une zone de fragilisation (5) délimitant une partie avant (6) s'étendant de ladite face avant (2) à ladite zone de fragilisation (5) et une partie arrière (7) formée du reste de la plaquette (1), b) détacher ladite partie arrière (7), la partie avant (6), c) répéter, si nécessaire, les étapes a) et b) sur la face arrière de ladite partie avant (6) jusqu'à ce que celle-ci présente l'épaisseur désirée pour constituer ladite couche mince auto-portée.
摘要翻译：
本发明涉及一种方法为了获得半导体材料的自支撑薄层，在其一个面上支撑至少一个元件和/或电子电路（3）从所述材料的晶片（1），所述材料具有支撑或预期用作载体的前表面（2）; 支撑至少一个部件和/或电子电路（3）和一个后面（4'）。这个过程是其显着之处在于它包括以下步骤：：a）植入原子种类; 所述晶片（1）的内部从其背面（4,4'），在所述晶片（1）的内侧，从其背面（4,4'），获得限制从所述前表面（2）延伸的前部（6）的脆化区（5）; 所述脆化区（5）和由所述晶片（1）的其余部分形成的后部（7），b）将所述后部（7），所述前部（6），c ）如果需要，将前部（6）的后面上的步骤a）和b）缩回到端部; 它表现出构成所述自磨薄层所需的厚度。

12. 发明申请

WO2009112894A8 SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER 审中-公开
公开(公告)号：WO2009112894A8
公开(公告)日：2009-09-17
申请号：PCT/IB2008/052203
申请日：2008-03-13
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ALLIBERT, Frédéric , GAUDIN, Gweltaz , LALLEMENT, Fabrice , LANDRU, Didier , LANDRY, Karine , SHAHEEN, Mohamad , MAZURE, Carlos
发明人： ALLIBERT, Frédéric , GAUDIN, Gweltaz , LALLEMENT, Fabrice , LANDRU, Didier , LANDRY, Karine , SHAHEEN, Mohamad , MAZURE, Carlos
IPC分类号： H01L29/78
摘要： The invention relates to a substrate comprising successively a base wafer (1), an insulating layer (2) and a top semiconductor layer (3), characterised in that the insulating layer (2) comprises at least a zone wherein the density of charges is in absolute value higher than 10 10 charges/cm 2 . The invention also relates to a process for making such a substrate.

13. 发明申请

WO2004077553A1 RELAXATION OF A THIN LAYER AT A HIGH TEMPERATURE AFTER ITS TRANSFER 审中-公开
标题翻译：转移后高温下的薄层放松
公开(公告)号：WO2004077553A1
公开(公告)日：2004-09-10
申请号：PCT/IB2004/000931
申请日：2004-03-01
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , GHYSELEN, Bruno , MAZURE, Carlos , ARENE, Emmanuel
发明人： GHYSELEN, Bruno , MAZURE, Carlos , ARENE, Emmanuel
IPC分类号： H01L21/763
CPC分类号： H01L21/76259 , H01L21/76254
摘要： The invention relates to a method for forming a relaxed or pseudo-relaxed layer on a substrate, the relaxed layer being in a material selected from among semiconductor materials, comprising the following steps: a) growing on a donor substrate (1) an elastically strained layer (2) constituted by at least a material chosen from among the semiconductor materials; b) forming on the strained layer (2), or on a receiver substrate (7), a vitreous layer (4) made of a material which is viscous above a viscosity temperature of more than about 900°C; c) bonding the receiver substrate (7) to the strained layer (2) by means of the vitreous layer (4) formed in step (b); d) removing the donor substrate (1), so as to form a structure (20) comprising the receiver substrate, the vitreous layer (4) and the strained layer (2); e) thermal treating the structure at a temperature close to or above the viscosity temperature, so as to relax at least a part of the constraints in the strained layer (2).
摘要翻译：本发明涉及一种用于在衬底上形成松弛或假松弛层的方法，所述松弛层是选自半导体材料的材料，包括以下步骤：a）在施主衬底（1）上生长弹性应变至少由选自半导体材料的材料构成的层（2） b）在应变层（2）上或在接收器基底（7）上形成玻璃质层（4），所述玻璃质层（4）由粘度高于大约900℃的粘度的材料制成; c）通过步骤（b）中形成的玻璃质层（4）将接收器衬底（7）接合到应变层（2）; d）去除施主衬底（1），以形成包括接收衬底，玻璃质层（4）和应变层（2）的结构（20）; e）在接近或高于粘度温度的温度下热处理该结构，以便使应变层（2）中的至少一部分约束松弛。

14. 发明申请

WO2004053961A1 MANUFACTURING PROCESS FOR A MULTILAYER STRUCTURE 审中-公开
标题翻译：多层结构的制造工艺
公开(公告)号：WO2004053961A1
公开(公告)日：2004-06-24
申请号：PCT/IB2003/006397
申请日：2003-12-05
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , MAZURE, Carlos
发明人： MAZURE, Carlos
IPC分类号： H01L21/20
CPC分类号： H01L21/76259 , H01L21/76254
摘要： The present invention relates to a production process for a multilayer structure made of semiconductor materials, said structure comprising a substrate (20) made of a first semiconductor material and a superficial thin layer made of a second semiconductor material, the two semiconductor materials having substantially different lattice parameters, characterised in that the process comprises the following steps: -producing a layer (110) comprising said superficial thin layer on a support substrate (100), -creating an embrittlement zone in the ensemble (10) formed by said support substrate and said deposited layer, -bonding said ensemble with a target substrate (20), -detaching at the level of this embrittlement zone, -treating the surface of the resulting structure.
摘要翻译：本发明涉及一种由半导体材料制成的多层结构的制造方法，所述结构包括由第一半导体材料制成的衬底（20）和由第二半导体材料制成的表面薄层，所述两种半导体材料具有显着不同晶格参数，其特征在于该方法包括以下步骤： - 在支撑衬底（100）上产生包含所述表面薄层的层（110）， - 在由所述支撑衬底形成的组合（10）中形成脆化区，以及所述沉积层将所述组合物与目标衬底（20）连接， - 在所述脆化区的水平面上取出，从而使所得结构的表面达到最佳状态。

15. 发明申请

WO2010015401A2 RELAXATION OF STRAINED LAYERS 审中-公开
标题翻译：应变层的松弛
公开(公告)号：WO2010015401A2
公开(公告)日：2010-02-11
申请号：PCT/EP2009/005694
申请日：2009-08-06
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES , LETERTRE, Fabrice , MAZURE, Carlos , KRAMES, Michael, R. , MCLAURIN, Melvin, B. , GARDNER, Nathan, F.
发明人： LETERTRE, Fabrice , MAZURE, Carlos , KRAMES, Michael, R. , MCLAURIN, Melvin, B. , GARDNER, Nathan, F.
IPC分类号： H01L21/324 , H01L21/20 , H01L33/00
CPC分类号： H01L21/2007 , H01L21/02422 , H01L21/02458 , H01L21/0254 , H01L21/02658 , H01L21/3245 , H01L33/0095
摘要： The present invention relates to a method for relaxing a strained material layer, comprising depositing a first low-viscosity layer comprising a first compliant material on the strained material layer, depositing a second low-viscosity layer comprising a second compliant material on the strained material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that reflow of the first and the second low-viscosity layers is caused thereby at least partly relaxing the strained material layer.
摘要翻译：本发明涉及一种松弛应变材料层的方法，包括在应变材料层上沉积包含第一顺应材料的第一低粘度层，在应变材料层上沉积包含第二柔性材料的第二低粘度层以形成第一夹层结构，并对第一夹层结构进行热处理，从而使第一和第二低粘度层的回流至少部分地松弛应变材料层。

16. 发明申请

WO2004044975A1 SEMICONDUCTOR STRUCTURE, AND METHODS FOR FABRICATING SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：WO2004044975A1
公开(公告)日：2004-05-27
申请号：PCT/EP2003/013697
申请日：2003-11-06
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES , GHYSELEN, Bruno , RAYSSAC, Olivier , AULNETTE, Cécile , MAZURE, Carlos
发明人： GHYSELEN, Bruno , RAYSSAC, Olivier , AULNETTE, Cécile , MAZURE, Carlos
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/76243 , H01L21/76259 , Y10S438/959 , Y10S438/977 , Y10S438/981
摘要： The invention relates to a method of producing a semiconductor structure, the method comprising: - forming in a first semiconductor material substrate (30) a first dielectric area (32a-c) of a first dielectric material having a first thickness and a second dielectric area (34a-b) having a second thickness, - assembling said first substrate with a second semiconductor material substrate (40), - fracturing the portion of the substrate in which the weakened layer is produced, and- thinning one or both substrates.
摘要翻译：本发明涉及一种制造半导体结构的方法，该方法包括：在第一半导体材料衬底（30）中形成具有第一厚度的第一介电材料的第一介电区域（32a-c）和第二介电区域（34a-b）， - 第二半导体材料基板（40）组装所述第一基板， - 破坏其中产生弱化层的基板的部分，以及 - 使一个或两个基板变薄。

17. 发明申请

WO2003062507A3 METHOD FOR MANUFACTURING A FREE-STANDING SUBSTRATE MADE OF MONOCRYSTALLINE SEMI-CONDUCTOR MATERIAL 审中-公开
公开(公告)号：WO2003062507A3
公开(公告)日：2003-07-31
申请号：PCT/EP2003/000693
申请日：2003-01-21
申请人： S.O.I.TEC SILICON INSULATOR TECHNOLOGIES , GHYSELEN, Bruno , LETERTRE, Fabrice , MAZURE, Carlos
发明人： GHYSELEN, Bruno , LETERTRE, Fabrice , MAZURE, Carlos
IPC分类号： C30B29/40
摘要： The invention relates to a method for manufacturing a free-standing substrate made of monocrystalline semi-conductor material.This method is characterized by the following steps comprising: - transferring of a thin nucleation layer (5, 5') onto a support (7) by creating between the two a removable bonding interface (9) ;- growing by epitaxy on said thin nucleation layer (5, 5'), a microcrystalline layer (10) of material intended to comprise said substrate, until it attains a sufficient thickness to be free-standing, while preserving the removable character of the bonding interface (9) ; the coefficients of thermal expansion of the material of the thick layer (10) and of the support material (7) being chosen to be different from each other, such that at the time of cooling of the assembly, the stresses induced by differential thermal expansion between the support material (7) and that of the thick layer (10) causing the removal of said nucleation layer (5, 5') and said monocrystalline thick layer (10) from said support (7) at the level of said removable bonding interface (9).

18. 发明申请

WO2010072278A1 METHOD OF FABRICATING A BACK-ILLUMINATED IMAGE SENSOR 审中-公开
标题翻译：制造背照明图像传感器的方法
公开(公告)号：WO2010072278A1
公开(公告)日：2010-07-01
申请号：PCT/EP2009/006845
申请日：2009-09-22
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES , BOURDELLE, Konstantin , MAZURE, Carlos
发明人： BOURDELLE, Konstantin , MAZURE, Carlos
IPC分类号： H01L27/146
CPC分类号： H01L27/14689 , H01L27/1464
摘要： The invention relates to a method of fabricating a back-illuminated image sensor comprising the steps of providing a first substrate comprising a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.
摘要翻译：本发明涉及一种制造背照式图像传感器的方法，包括以下步骤：提供包括半导体层，特别是硅层的第一衬底，在半导体层上形成电子器件结构，并且仅仅掺杂半导体层。通过这样做，可以实现改进的光电二极管的掺杂剂分布和电性能，使得最终产品，即图像传感器具有更好的质量。

19. 发明申请

WO2013045970A1 PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS 审中-公开
标题翻译：具有多个独立栅极晶体管的PSEUDO-INVERTER电路
公开(公告)号：WO2013045970A1
公开(公告)日：2013-04-04
申请号：PCT/IB2011/002823
申请日：2011-09-30
申请人： SOITEC , MAZURE, Carlos , FERRANT, Richard , NGUYEN, Bich-Yen
发明人： MAZURE, Carlos , FERRANT, Richard , NGUYEN, Bich-Yen
IPC分类号： G11C8/08 , G11C11/408 , H03K19/20
CPC分类号： H03K19/20 , G11C8/08 , G11C11/4085
摘要： The invention relates to a a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G 1P , G 1N ) and a second (G 2P , G 2N ) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G 2p , G 2N ).
摘要翻译：本发明涉及一种电路，包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作（G2p，G2N）。

20. 发明申请

WO2007133358A2 SEMICONDUCTOR BUFFER STRUCTURES 审中-公开
公开(公告)号：WO2007133358A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/008879
申请日：2007-04-09
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES, S.A. , CODY, Nyles, W. , ARENA, Chantel , TOMASINI, Pierre , MAZURE, Carlos
发明人： CODY, Nyles, W. , ARENA, Chantel , TOMASINI, Pierre , MAZURE, Carlos
IPC分类号： C23C16/22 , C23C16/455 , C30B29/02 , C30B25/14
CPC分类号： C23C16/22 , C23C16/24 , C23C16/45523 , C30B25/165 , C30B29/52
摘要： Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.
摘要翻译：通过增强位错滑行，减少厚度梯度缓冲层穿透位错的堆积。在形成渐变的SiGe缓冲层期间，从硅前体和锗前体的SiGe的沉积被中断一次或多次，其中停止向硅衬底的硅前驱体的流动，同时锗前体流向保持底物。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式