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1. 发明申请

WO2013045970A1 PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS 审中-公开
标题翻译：具有多个独立栅极晶体管的PSEUDO-INVERTER电路
公开(公告)号：WO2013045970A1
公开(公告)日：2013-04-04
申请号：PCT/IB2011/002823
申请日：2011-09-30
申请人： SOITEC , MAZURE, Carlos , FERRANT, Richard , NGUYEN, Bich-Yen
发明人： MAZURE, Carlos , FERRANT, Richard , NGUYEN, Bich-Yen
IPC分类号： G11C8/08 , G11C11/408 , H03K19/20
CPC分类号： H03K19/20 , G11C8/08 , G11C11/4085
摘要： The invention relates to a a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G 1P , G 1N ) and a second (G 2P , G 2N ) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G 2p , G 2N ).
摘要翻译：本发明涉及一种电路，包括与用于施加电源电位的第一和第二端子之间的第二类型沟道的晶体管串联的第一类型沟道的晶体管，每个晶体管是至少具有多栅极晶体管第一（G1P，G1N）和第二（G2P，G2N）独立控制门，其特征在于，至少一个晶体管被配置为在施加到其第二控制栅极的第二栅极信号的作用下以耗尽模式工作（G2p，G2N）。

2. 发明申请

WO2011123199A1 BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME 审中-公开
标题翻译：粘结半导体结构及其形成方法
公开(公告)号：WO2011123199A1
公开(公告)日：2011-10-06
申请号：PCT/US2011/025647
申请日：2011-02-22
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , MAZURE, Carlos , NGUYEN, Bich-Yen , SADAKA, Mariam
发明人： MAZURE, Carlos , NGUYEN, Bich-Yen , SADAKA, Mariam
IPC分类号： H01L27/06 , H01L21/822
CPC分类号： H01L27/0688 , H01L21/02532 , H01L21/0262 , H01L21/02667 , H01L21/187 , H01L21/8221 , H01L2924/00011 , H01L2224/80001
摘要： Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.
摘要翻译：形成半导体结构的方法包括将施主结构的部分（116a）转移到包括至少一个非平面表面的经处理的半导体结构（102）。可以在结合的半导体结构的至少一个非平面表面上形成非晶膜（144），并且非晶膜可以被平坦化以形成一个或多个平坦化表面。半导体结构包括具有至少一个非平面表面的键合半导体结构和设置在所述至少一个非平面表面上的非晶膜。键合的半导体结构可以包括处理的半导体结构和附接到处理的半导体结构的非平面表面的单晶体施主结构的一部分。

3. 发明申请

WO2010002509A1 SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：半导体结构
公开(公告)号：WO2010002509A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/044372
申请日：2009-05-18
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , NGUYEN, Bich-Yen , MAZURE, Carlos
发明人： NGUYEN, Bich-Yen , MAZURE, Carlos
IPC分类号： H01L27/12 , H01L21/70
CPC分类号： H01L21/76254 , H01L21/76256
摘要： In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate.
摘要翻译：在优选实施例中，本发明提供一种半导体结构，其具有半导电支撑件，布置在支撑件的一部分上的绝缘层和布置在绝缘层上的半导电表面层。电子器件可以形成在表面层中，也可以形成在衬底的半导体本体区域的未被绝缘层覆盖的露出部分中。本发明还提供了制造这样的半导体结构的方法，其从包括布置在连续绝缘层上的半导电表面层的衬底开始，两者均布置在半导电支撑件上，通过将至少一个选定区域基板，以形成基板的暴露的半导体本体区域。

4. 发明申请

WO2013021255A1 METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES IN 3D INTEGRATION PROCESSES USING RECOVERABLE SUBSTRATES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS 审中-公开
标题翻译：使用可恢复基板在3D集成工艺中形成结合的半导体结构的方法和通过这种方法形成的结合的半导体结构
公开(公告)号：WO2013021255A1
公开(公告)日：2013-02-14
申请号：PCT/IB2012/001494
申请日：2012-08-02
申请人： SOITEC , SADAKA, Mariam , NGUYEN, Bich-Yen
发明人： SADAKA, Mariam , NGUYEN, Bich-Yen
IPC分类号： H01L21/683 , H01L25/065 , H01L21/60 , H01L21/768 , H01L23/14 , H01L21/48
CPC分类号： H01L21/6835 , H01L21/76898 , H01L24/03 , H01L24/06 , H01L24/80 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/05009 , H01L2224/05025 , H01L2224/80006 , H01L2224/80095 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/95001 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06572 , H01L2924/01029 , H01L2924/12041 , H01L2924/12043 , H01L2924/1461 , H01L2924/3511 , H01L2924/00
摘要： Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods.
摘要翻译：形成键合的半导体结构的方法包括通过晶片互连通过第一衬底结构的材料层形成，在材料层上结合一个或多个半导体结构，以及将半导体结构与贯穿晶片互连电连接。第二衬底结构可以在与第一衬底结构相对的一侧上结合在经处理的半导体结构上。然后可以去除第一衬底结构的一部分，留下其中附着有经处理的半导体结构的贯穿晶片互连的材料层。然后至少一个贯穿晶片互连可以电耦合到另一结构的导电特征，之后可以去除第二衬底结构。使用这种方法形成结合的半导体结构。

5. 发明申请

WO2013021251A1 METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING INTERCONNECT LAYERS HAVING ONE OR MORE OF ELECTRICAL, OPTICAL, AND FLUIDIC INTERCONNECTS THEREIN, AND BONDED SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS 审中-公开
标题翻译：形成粘结半导体结构的方法，其中包括具有电气，光学和流体互连的一个或多个的互连层，以及使用这种方法形成的结合的半导体结构
公开(公告)号：WO2013021251A1
公开(公告)日：2013-02-14
申请号：PCT/IB2012/001482
申请日：2012-07-31
申请人： SOITEC , NGUYEN, Bich-Yen , SADAK, Mariam
发明人： NGUYEN, Bich-Yen , SADAK, Mariam
IPC分类号： H01L21/98 , H01L21/683
CPC分类号： H01L25/50 , G02B6/43 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/367 , H01L23/473 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/95 , H01L24/96 , H01L25/0652 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68381 , H01L2224/0231 , H01L2224/02379 , H01L2224/0401 , H01L2224/05009 , H01L2224/05647 , H01L2224/05687 , H01L2224/08145 , H01L2224/08146 , H01L2224/08225 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/29187 , H01L2224/32145 , H01L2224/32146 , H01L2224/80006 , H01L2224/802 , H01L2224/80201 , H01L2224/80203 , H01L2224/80447 , H01L2224/80487 , H01L2224/80895 , H01L2224/80896 , H01L2224/81191 , H01L2224/81815 , H01L2224/83005 , H01L2224/83191 , H01L2224/83193 , H01L2224/92 , H01L2224/9202 , H01L2224/95 , H01L2224/96 , H01L2225/06513 , H01L2225/06527 , H01L2225/06534 , H01L2225/06541 , H01L2225/06589 , H01L2924/12041 , H01L2924/12043 , H01L2924/00014 , H01L2924/00012 , H01L2924/05442 , H01L2924/05042 , H01L2924/014 , H01L2224/80 , H01L2224/11 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： Methods of forming bonded semiconductor structures include providing a substrate structure including a relatively thin layer (102) of material on a thicker substrate body (104), and forming a plurality of through wafer interconnects (112) through the thin layer of material. A first semiconductor structure (132A-132F)may be bonded over the thin layer of material, and at least one conductive feature (134) of the first semiconductor structure may be electrically coupled with at least one of the through wafer interconnects. A transferred layer of material (212) may be provided over the first semiconductor structure on a side thereof opposite the first substrate structure, and at least one of an electrical interconnect (302), an optical interconnect (402), and a fluidic interconnect (504) may be formed in the transferred layer of material. A second semiconductor structure (322,422) may be provided over the transferred layer of material on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are fabricated using such methods.
摘要翻译：形成键合的半导体结构的方法包括在较厚的衬底主体（104）上提供包括相对较薄的材料层（102）的衬底结构，以及通过薄的材料层形成多个通过晶片的互连（112）。第一半导体结构（132A-132F）可以结合在材料的薄层上，并且第一半导体结构的至少一个导电特征（134）可以与透晶片互连中的至少一个电耦合。转移的材料层（212）可以在第一半导体结构的与第一衬底结构相对的一侧上提供，并且电互连（302），光学互连（402）和流体互连（ 504）可以形成在转移的材料层中。第二半导体结构（322,422）可以设置在与第一半导体结构相对的一侧上的转移的材料层上。使用这种方法制造粘合的半导体结构。

6. 发明申请

WO2006107419A3 METHOD OF MAKING A DUAL STRAINED CHANNEL SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2006107419A3
公开(公告)日：2006-10-12
申请号：PCT/US2006/005471
申请日：2006-02-16
申请人： FREESCALE SEMICONDUCTOR, INC. , SADAKA, Mariam G. , BARR, Alexander L. , JOVANOVIC, Dejan , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn G. , WHITE, Ted R.
发明人： SADAKA, Mariam G. , BARR, Alexander L. , JOVANOVIC, Dejan , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn G. , WHITE, Ted R.
IPC分类号： H01L21/8238
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device (10) includes integrating strained Si (16) and compressed SiGe (28) with trench isolation (24) for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

7. 发明申请

WO2006039037A1 DOUBLE GATE DEVICE HAVING A STRAINED CHANNEL 审中-公开
标题翻译：具有应变通道的双门设备
公开(公告)号：WO2006039037A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/031000
申请日：2005-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , THEAN, Voon-Yew , SADAKA, Mariam, G. , WHITE, Ted, R. , BARR, Alexander, L. , KOLAGUNTA, Venkat, R. , NGUYEN, Bich-Yen , VARTANIAN, Victor, H. , ZHANG, Da
发明人： THEAN, Voon-Yew , SADAKA, Mariam, G. , WHITE, Ted, R. , BARR, Alexander, L. , KOLAGUNTA, Venkat, R. , NGUYEN, Bich-Yen , VARTANIAN, Victor, H. , ZHANG, Da
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66628 , H01L29/66742 , H01L29/7842 , H01L29/78621 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

8. 发明申请

WO2006033746A3 METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A METAL LAYER 审中-公开
公开(公告)号：WO2006033746A3
公开(公告)日：2006-03-30
申请号：PCT/US2005/029772
申请日：2005-08-23
申请人： FREESCALE SEMICONDUCTOR, INC. , STEVENS, Tab A. , GOOLSBY, Brian J. , NGUYEN, Bich-Yen , THEAN, Voon-Yew
发明人： STEVENS, Tab A. , GOOLSBY, Brian J. , NGUYEN, Bich-Yen , THEAN, Voon-Yew
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461
摘要： A metal layer (24) is formed over a metal oxide (14), where the metal oxide is formed over a semiconductor substrate (12). A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings (26) at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer (22) is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.

9. 发明申请

WO2005034230A1 SEMICONDUCTOR STRUCTURE WITH DIFFERENT LATTICE CONSTANT MATERIALS AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：具有不同厚度常数材料的半导体结构及其形成方法
公开(公告)号：WO2005034230A1
公开(公告)日：2005-04-14
申请号：PCT/US2004/031516
申请日：2004-09-27
申请人： FREESCALE SEMICONDUCTOR, INC. , LIU, Chun-Li , BARR, Alexander, L. , GRANT, John, M. , NGUYEN, Bich-Yen , ORLOWSKI, Marius, K. , STEPHENS, Tab, A. , WHITE, Ted, R. , THOMAS, Shawn, G.
发明人： LIU, Chun-Li , BARR, Alexander, L. , GRANT, John, M. , NGUYEN, Bich-Yen , ORLOWSKI, Marius, K. , STEPHENS, Tab, A. , WHITE, Ted, R. , THOMAS, Shawn, G.
IPC分类号： H01L21/335
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L29/04 , H01L29/665 , H01L29/7833
摘要： A semiconductor structure (10) includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer (34) overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material (22) with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also enclosed.
摘要翻译：半导体结构（10）包括具有第一晶格常数的第一松弛半导体材料的衬底。半导体器件层（34）覆盖在衬底上，其中半导体器件层包括具有不同于第一晶格常数的第二晶格常数的第二松弛半导体材料（22）。另外，在基板和半导体器件层之间插入电介质层，其中介电层介于基板和半导体器件层之间，其中介电层包括布置在电介质层内的过渡区，用于在第一晶格常数和第二晶格常数。编程的过渡区域包括多个层，多个层中相邻的层具有不同的晶格常数，其中相邻的层之一具有超过形成缺陷所需的第一临界厚度的第一厚度，而另一层具有第二厚度不超过第二临界厚度。多个层中的每个相邻层形成用于促进过渡区中的缺陷迁移到并终止于编程的过渡区的边缘的界面。也包括制作该方法的方法。

10. 发明申请

WO2010002508A1 SUBSTRATE COMPRISING DIFFERENT TYPES OF SURFACES AND METHOD FOR OBTAINING SUCH SUBSTRATES 审中-公开
标题翻译：包含不同类型表面的基板和用于获得这种基板的方法
公开(公告)号：WO2010002508A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/044365
申请日：2009-05-18
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , NGUYEN, Bich-Yen
发明人： NGUYEN, Bich-Yen
IPC分类号： H01L27/04
CPC分类号： H01L21/76254 , H01L21/76256
摘要： A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.
摘要翻译：具有较大结晶缺陷密度的支撑体，设置在支撑体正面的第一区域上的绝缘层和设置在绝缘层上的表面层。可以至少在支撑体的前表面的第二区域上设置附加层，其厚度足以埋设支撑体的结晶缺陷。衬底还可以包括布置在支撑体的前表面的至少第一区域之间，在支撑体和绝缘层之间的外延层。此外，通过在表层的第一区域上形成掩模层并除去由掩模层未覆盖的第二区域中的表层和绝缘层来制造衬底的方法。附加层形成在第二区域中，然后平坦化。

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