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11. 发明申请

WO2004042831A3 RADIATION-EMITTING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：辐射发射半导体器件及其制造方法
公开(公告)号：WO2004042831A3
公开(公告)日：2005-03-31
申请号：PCT/IB0304881
申请日：2003-10-31
申请人： KONINKL PHILIPS ELECTRONICS NV , WOERLEE PIERRE H , T HOOFT GERT W , HOLLEMAN JISK
发明人： WOERLEE PIERRE H , T HOOFT GERT W , HOLLEMAN JISK
IPC分类号： H01L27/15 , H01L33/34 , H01L33/00
CPC分类号： H01L33/34 , H01L27/15
摘要： Radiation-emitting semiconductor device and method of manufacturing such a device. The invention relates to a radiation-emitting semiconductor device (10) comprising a silicon-containing semiconductor body (1) and a substrate (2), which semiconductor body (1) comprises a lateral semiconductor diode positioned on an insulating layer (7) which separates the diode from the substrate (2). The lateral semiconductor diode comprises a first semiconductor region (3) of a first conductivity type and with a first doping concentration, a second semiconductor region (4) of the first or a second conductivity type opposite to the first conductivity type and with a second doping concentration which is lower than the first doping concentration, and a third semiconductor region (5) of the second conductivity type and with a third doping concentration which is higher than the second doping concentration, the first and the third region (3, 5) each being provided with a connection region (6, 8), and, during operation, radiation (S) being generated in the second region (4) due to recombination of charge carriers injected therein from the first and the third region (3, 5). According to the invention, the second semiconductor region (4) comprises a central part (4A) which is surrounded by a further part (4B) the bandgap of which is larger than the bandgap of the central part (4A). In this way, the radiation yield is increased in an indirect semiconductor material such as silicon in the central part (4A) as translation of the relatively long-living charge carriers towards a non-radiative recombination center is limited because of the barriers in the valence and conduction band in the further part (4B). Preferably, the bandgap in the further part (4B) is made larger in that the thickness of said part (4B) is so small that quantum size effects occur therein, while the central part (4A) has a thickness which is so large that such effects do not occur or substantially do not occur.
摘要翻译：辐射发射半导体器件及其制造方法。本发明涉及一种包括含硅半导体主体（1）和基板（2）的辐射发射半导体器件（10），该半导体本体（1）包括位于绝缘层（7）上的横向半导体二极管将二极管与衬底（2）分开。横向半导体二极管包括第一导电类型和第一掺杂浓度的第一半导体区域（3），与第一导电类型相反的第一或第二导电类型的第二半导体区域（4）和第二掺杂浓度低于第一掺杂浓度的浓度，以及第二导电类型的第三半导体区域（5）和高于第二掺杂浓度的第三掺杂浓度，第一和第三区域（3,5）各自设置有连接区域（6,8），并且在操作期间，由于从第一和第三区域（3,5）注入的电荷载流子的复合，在第二区域（4）中产生辐射（S）。根据本发明，第二半导体区域（4）包括由带隙大于中心部分（4A）的带隙的另一部分（4B）包围的中心部分（4A）。以这种方式，中间部分（4A）中的间接半导体材料（例如硅）的辐射产量增加，因为相对较长寿命的电荷载流子朝向非辐射复合中心的平移由于价态的障碍而受到限制和另一部分（4B）中的导带。优选地，使另一部分（4B）中的带隙变得更大，因为所述部分（4B）的厚度如此小以致其中出现量子尺寸效应，而中心部分（4A）具有如此大的厚度效果不会发生或基本不发生。

12. 发明申请

WO2007034384A2 SINGLE THRESHOLD AND SINGLE CONDUCTIVITY TYPE LOGIC 审中-公开
标题翻译：单路和单电导型逻辑
公开(公告)号：WO2007034384A2
公开(公告)日：2007-03-29
申请号：PCT/IB2006053281
申请日：2006-09-14
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN ACHT VICTOR M G , LAMBERT NICOLAAS , MIJIRITSKII ANDREI , WOERLEE PIERRE H
发明人： VAN ACHT VICTOR M G , LAMBERT NICOLAAS , MIJIRITSKII ANDREI , WOERLEE PIERRE H
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current pathes being coupled to a common note that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主要的电流裸片耦合到形成逻辑组件（400）的输出的公共音符。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

13. 发明申请

WO2007066276A3 AN ELECTRONIC CIRCUIT WITH A MEMORY MATRIX 审中-公开
标题翻译：具有存储矩阵的电子电路
公开(公告)号：WO2007066276A3
公开(公告)日：2007-10-11
申请号：PCT/IB2006054583
申请日：2006-12-04
申请人： NXP BV , LAMBERT NICOLAAS , VAN ACHT VICTOR M G , WOERLEE PIERRE H , MIJIRITSKII ANDREI
发明人： LAMBERT NICOLAAS , VAN ACHT VICTOR M G , WOERLEE PIERRE H , MIJIRITSKII ANDREI
IPC分类号： G11C16/02 , H01L27/105
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.
摘要翻译：电子电路包括具有存储单元（16）的行和列的存储矩阵（60）。为每行设置第一行导体（10,12）。提供第二行导体（12）用于连续重叠相邻行对。为每个列提供列导体（14）。每个存储单元（16）包括存取晶体管（160），节点（166）和第一和第二电阻性存储元件（162,164）。存取晶体管（160）优选地是垂直晶体管，其具有耦合到存储单元（16）的行的第一行导体（10）的控制电极，耦合在用于列的列导体（14）之间的主电流通道的存储单元（160）和节点（166）。第一和第二电阻性存储器元件（162,164）耦合在用于存储器单元所属的行对的节点（166）和第二行导体（12）之间。

14. 发明申请

WO9965070A3 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A MOS TRANSISTOR 审中-公开
标题翻译：制造包含MOS晶体管的半导体器件的方法
公开(公告)号：WO9965070A3
公开(公告)日：2000-04-27
申请号：PCT/IB9901003
申请日：1999-06-03
申请人： KONINKL PHILIPS ELECTRONICS NV , PHILIPS SVENSKA AB
发明人： SCHMITZ JURRIAAN , WOERLEE PIERRE H
IPC分类号： H01L21/225 , H01L21/265 , H01L21/266 , H01L21/3115 , H01L21/336 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/6659 , H01L21/2255 , H01L21/31155
摘要： The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11) which is positioned above a gate oxide (1A) is provided with a dielectric layer (1B) at the location where a source (3) and drain (4) are to be formed, which dielectric layer includes a thermal oxide layer (1B) to be formed as the starting layer. The source (3) and/or drain (4) is/are provided with LDD regions (3A, 4A) and the remaining parts (3B, 4B) of the source (3) and drain (4) are provided by an ion implantation (I1) of doping atoms into the silicon substrate (10, 11). A MOST obtained in this way still suffers from so-called short-channel effects, resulting in a substantial dependence of the threshold voltage upon the length of the gate electrode (2), in particular in the case of very short lengths of the gate electrode (2). In a method according to the invention, the LDD regions (3A, 4A) are made as follows: in a first step, suitable doping atoms (D) are implanted into the dielectric layer (1B), in a second ion implantation (I2), and subsequently in a second step, a part of the doping atoms (D) is diffused from the dielectric layer (1B) into the silicon substrate (10, 11), whereby the LDD regions (3A, 4A) are formed. This method enables a MOST with excellent properties to be obtained, for example with a flatter profile of the threshold voltage versus the gate-electrode (2) length (curve 130) than in conventionally made MOSTs (curve 131). This result is obtained in a simple and reproducible manner.
摘要翻译：本发明涉及制造（水平）MOST的方法，例如在（BI）CMOS IC中使用的MOST。在栅电极（2）的任一侧，位于栅极氧化物（1A）上方的硅衬底（10,11）的表面在源（3）的位置处设置有电介质层（1B）并形成漏极（4），该介电层包括要作为起始层形成的热氧化物层（1B）。源极（3）和/或漏极（4）设置有LDD区域（3A，4A），源极（3）和漏极（4）的其余部分（3B，4B）由离子注入（I1）掺杂原子到硅衬底（10,11）中。以这种方式获得的MOST仍然受到所谓的短沟道效应的影响，导致阈值电压对栅电极（2）的长度的实质依赖性，特别是在非常短的栅电极的长度的情况下（2）。在根据本发明的方法中，LDD区域（3A，4A）制成如下：在第一步骤中，在第二离子注入（I2）中，将合适的掺杂原子（D）注入电介质层（1B），随后在第二步骤中，一部分掺杂原子（D）从电介质层（1B）扩散到硅衬底（10,11）中，由此形成LDD区（3A，4A）。该方法使得能够获得具有优异性能的MOST，例如与常规制造的MOST（曲线131）相比，阈值电压相对于栅电极（2）长度（曲线130）的平坦轮廓。该结果以简单且可再现的方式获得。

15. 发明申请

WO0019509A3 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：用场效应晶体管制造半导体器件的方法
公开(公告)号：WO0019509A3
公开(公告)日：2000-08-03
申请号：PCT/EP9906699
申请日：1999-09-09
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： SCHMITZ JURRIAAN , WOERLEE PIERRE H , MONTREE ANDREAS H
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28079 , H01L29/495 , H01L29/66545
摘要： In the known replacement gate process, the relatively high-ohmic poly gate is replaced by a low-ohmic metal gate by depositing a thick oxide layer and subsequently planarizing this layer by CMP until the gate is reached, which gate can be selectively removed and replaced by a metal gate. The process is simplified considerably by providing the gate structure as a stack of a dummy poly gate (4) and a nitride layer (5) on top of the poly gate. When, during the CMP, the nitride layer is reached, the CMP is stopped, thereby precluding an attack on the poly. The nitride and the poly are selectively removed relative to the oxide layer (10).
摘要翻译：在已知的替代栅极工艺中，通过沉积厚的氧化物层，然后通过CMP平坦化该层，直到达到栅极，该相对高欧姆的多晶硅栅极被低欧姆金属栅极代替，该栅极可被选择性地去除和替换由金属门。通过将栅极结构设置为多晶硅栅极顶部的虚设多晶硅栅极（4）和氮化物层（5）的叠层，可大大简化工艺。当在CMP期间达到氮化物层时，停止CMP，从而排除对聚合物的攻击。相对于氧化物层（10）选择性地去除氮化物和多晶硅。

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