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11. 发明申请

WO2008109199A9 METHODS FOR FORMING NONVOLATILE MEMORY ELEMENTS WITH RESISTIVE-SWITCHING METAL OXIDES 审中-公开
标题翻译：形成具有电阻开关金属氧化物的非易失性存储元件的方法
公开(公告)号：WO2008109199A9
公开(公告)日：2008-10-30
申请号：PCT/US2008052082
申请日：2008-01-25
申请人： INTERMOLECULAR INC , KUMAR NITIN , TONG JINHONG , LANG CHI-I , CHIANG TONY , PHATAK PRASHANT B
发明人： KUMAR NITIN , TONG JINHONG , LANG CHI-I , CHIANG TONY , PHATAK PRASHANT B
IPC分类号： H01L27/115
CPC分类号： H01L27/101 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1608
摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal- containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal suicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.
摘要翻译：提供具有电阻开关金属氧化物的非易失性存储元件。非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。含金属材料可以被氧化以形成电阻式开关金属氧化物。当施加热量时，含硅材料中的硅与含金属材料中的金属反应。这形成用于非易失性存储元件的金属硅化物下电极。上部电极可以沉积在金属氧化物的顶部。由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

12. 发明申请

WO02073689A3 INTEGRATED BARRIER LAYER STRUCTURE FOR COPPER CONTACT LEVEL METALLIZATION 审中-公开
标题翻译：用于铜接触层级金属化的集成阻挡层结构
公开(公告)号：WO02073689A3
公开(公告)日：2003-04-10
申请号：PCT/US0207276
申请日：2002-03-08
申请人： APPLIED MATERIALS INC
发明人： CHIANG TONY , DING PEIJUN , CHIN BARRY L
IPC分类号： H01L21/285 , H01L21/768
CPC分类号： H01L21/76855 , H01L21/2855 , H01L21/28556 , H01L21/76843
摘要： A method for forming an integrated barrier layer structure that is compatible with copper (Cu) metallization schemes for integrated circuit fabrication is disclosed. In one aspect, an integrated circuit is metallized by forming an integrated barrier layer structure on a silicon substrate followed by deposition of one or more copper (Cu) layers. The integrated barrier layer structure includes one or more barrier layers selected from tantalum (Ta), tantalum nitride (TaNx), tungsten (W), and tungsten nitride (WNx) conformably deposited on the silicon substrate. After the one or more barrier layers are deposited on the silicon substrate, the silicon substrate is heated to form a silicide layer at the interface between the silicon substrate and the barrier layers.
摘要翻译：公开了一种与集成电路制造用铜（Cu）金属化方案兼容的集成阻挡层结构的形成方法。在一个方面中，通过在硅衬底上形成集成的阻挡层结构，然后沉积一个或多个铜（Cu）层，从而对集成电路进行金属化。集成阻挡层结构包括从硅（Ta），氮化钽（TaNx），钨（W）和钨氮化物（WNx）中选择的一个或多个势垒层，其顺应地沉积在硅衬底上。在一个或多个阻挡层沉积在硅衬底上之后，硅衬底被加热以在硅衬底和阻挡层之间的界面处形成硅化物层。

13. 发明申请

WO0211187A3 METHOD AND APPARATUS FOR DEPOSITING A TANTALUM-CONTAINING LAYER ON A SUBSTRATE 审中-公开
标题翻译：在基材上沉积含有钽酸盐的层的方法和装置
公开(公告)号：WO0211187A3
公开(公告)日：2002-12-19
申请号：PCT/US0123702
申请日：2001-07-30
申请人： APPLIED MATERIALS INC
发明人： MILLER MICHAEL A , CHIANG TONY , DING PEIJUN , FU JIANMING , TANG HOWARD
IPC分类号： C23C14/06 , C23C14/35 , C30B25/02 , H01J37/34 , H01L21/285 , H01L21/768
CPC分类号： H01L21/76843 , C23C14/0641 , C23C14/35 , C30B25/02 , C30B29/38 , H01J37/3408 , H01J37/3441 , H01L21/28568
摘要： A method of forming a tantalum-containing layer on a substrate is described. The tantalum-containing layer is formed using a physical vapor deposition technique wherein a magnetic field in conjunction with an electric field function to confine material sputtered from a tantalum-containing target within a reaction zone of a deposition chamber. The electric field is generated by applying a power of at least 8 kilowatts to the tantalum-containing target. The magnetic field is generated from a magnetron including a first magnetic pole of a first magnetic polarity surrounded by a second magnetic pole of a second magnetic polarity opposite the first magnetic polarity. The first magnetic pole preferably has a magnetic flux at least about 30% greater than a magnetic flux of the second magnetic pole. The tantalum-containing layer deposition method is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, an interconnect structure is formed.
摘要翻译：描述了在基板上形成含钽层的方法。使用物理气相沉积技术形成含钽层，其中与电场结合的磁场用于限制从沉积室的反应区域内的含钽靶溅射的材料。通过将至少8千瓦的功率施加到含钽靶产生电场。该磁场由磁控管产生，该磁控管包括由与第一磁极性相反的第二磁极的第二磁极包围的第一磁极的第一磁极。第一磁极优选地具有比第二磁极的磁通大至少大约30％的磁通量。含钽层沉积方法与集成电路制造工艺兼容。在一个集成电路制造工艺中，形成互连结构。

14. 发明申请

WO0029636A9 HIGH PURITY TANTALUM TARGETS FOR SPUTTERING 审中-公开
标题翻译：高纯度TANTALUM目标用于喷射
公开(公告)号：WO0029636A9
公开(公告)日：2001-07-19
申请号：PCT/US9926290
申请日：1999-11-05
申请人： APPLIED MATERIALS INC
发明人： SUN BINXI , CHIANG TONY , PAVATE VIKRAM , DING PEIJUN , CHIN BARRY , SUNDARRAJAN ARVIND , HONG ILYOUNG RICHARD
IPC分类号： C23C14/06 , C23C14/14 , C23C14/34 , H01L21/28 , H01L21/285 , H01L21/768 , C23C14/16 , H01L21/283
CPC分类号： H01L21/28568 , C23C14/0641 , C23C14/14 , C23C14/3414 , H01L21/76838
摘要： Improved tantalum-containing barrier layers are obtained by sputter depositing tantalum and/or tantalum nitride from a target having a low contaminant level, i.e., a metallic contaminant content below about 30 ppm by weight; or a niobium contaminant content below about 50 ppm by weight, preferably below 10 ppm, a molybdenum content below about 10 ppm by weight, a gold contaminants below about 15 ppm by weight, and a tungsten content below about 10 ppm by weight. Medium time to failure of copper capacitors including these layers is increased over the use of conventional tantalum targets which have higher amounts of contaminants.
摘要翻译：通过从具有低污染物水平的目标溅射沉积钽和/或氮化钽获得改进的含钽阻挡层，即金属污染物含量低于约30ppm重量; 或铌污染物含量低于约50ppm，优选低于10ppm，低于约10ppm重量的钼含量，低于约15ppm重量的金污染物以及低于约10ppm重量的钨含量。包括这些层在内的铜电容器的中等时间比使用具有较高量污染物的常规钽靶增加。

15. 发明申请

WO0007236A3 METHOD AND APPARATUS FOR FORMING IMPROVED METAL INTERCONNECTS 审中-公开
标题翻译：用于形成改进的金属互连的方法和设备
公开(公告)号：WO0007236A3
公开(公告)日：2000-06-22
申请号：PCT/US9916887
申请日：1999-07-26
申请人： APPLIED MATERIALS INC
发明人： HASHIM IMRAN , CHIANG TONY , CHIN BARRY
IPC分类号： H01L21/285 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter-etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.
摘要翻译：公开了形成没有通孔到通孔泄漏电流并具有低电阻的铜互连的方法。在第一方面中，在氧化铜溅射蚀刻之前在第一金属层上沉积阻挡层以防止铜原子到达层间电介质并在其中形成通孔到通孔漏电流路径。在第二方面中，在溅射蚀刻之前，在第一金属层上沉积覆盖电介质阻挡层。在溅射蚀刻期间，覆盖电介质阻挡层重新分布在层间电介质的侧壁上，防止溅射蚀刻的铜原子到达层间电介质并在其中形成通孔到通孔泄漏路径。在第三方面中，在溅射蚀刻之前，在第一金属层上沉积覆盖电介质阻挡层和阻挡层以防止在溅射蚀刻期间产生的铜原子到达层间电介质并形成通孔到通孔泄漏路径在其中。

16. 发明申请

WO0029636A2 IMPROVED TANTALUM-CONTAINING BARRIER LAYERS FOR COPPER USING HIGH PURITY TANTALUM TARGETS FOR SPUTTERING 审中-公开
标题翻译：用于溅射的高纯度TANTALUM目标铜的改进的含TANTALUM的BARRIER层
公开(公告)号：WO0029636A2
公开(公告)日：2000-05-25
申请号：PCT/US9926290
申请日：1999-11-05
申请人： APPLIED MATERIALS INC
发明人： SUN BINXI , CHIANG TONY , PAVATE VIKRAM , DING PEIJUN , CHIN BARRY , SUNDARRAJAN ARVIND , HONG ILYOUNG RICHARD
IPC分类号： C23C14/06 , C23C14/14 , C23C14/34 , H01L21/28 , H01L21/285 , H01L21/768 , C23C14/16 , H01L21/283
CPC分类号： H01L21/28568 , C23C14/0641 , C23C14/14 , C23C14/3414 , H01L21/76838
摘要： Improved tantalum-containing barrier layers are obtained by sputter depositing tantalum and/or tantalum nitride from a target having a low contaminant level, i.e., a metallic contaminant content below about 30 ppm by weight; or a niobium contaminant content below about 50 ppm by weight, preferably below 10 ppm, a molybdenum content below about 10 ppm by weight, a gold contaminants below about 15 ppm by weight, and a tungsten content below about 10 ppm by weight. Medium time to failure of copper capacitors including these layers is increased over the use of conventional tantalum targets which have higher amounts of contaminants.
摘要翻译：通过从具有低污染物水平的目标溅射沉积钽和/或氮化钽获得改进的含钽阻挡层，即金属污染物含量低于约30ppm重量; 或铌污染物含量低于约50ppm，优选低于10ppm，低于约10ppm重量的钼含量，低于约15ppm重量的金污染物以及低于约10ppm重量的钨含量。包括这些层在内的铜电容器的中等时间比使用具有较高量污染物的常规钽靶增加。

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