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    • 1. 发明申请
    • INTEGRATED BARRIER LAYER STRUCTURE FOR COPPER CONTACT LEVEL METALLIZATION
    • 用于铜接触层级金属化的集成阻挡层结构
    • WO02073689A3
    • 2003-04-10
    • PCT/US0207276
    • 2002-03-08
    • APPLIED MATERIALS INC
    • CHIANG TONYDING PEIJUNCHIN BARRY L
    • H01L21/285H01L21/768
    • H01L21/76855H01L21/2855H01L21/28556H01L21/76843
    • A method for forming an integrated barrier layer structure that is compatible with copper (Cu) metallization schemes for integrated circuit fabrication is disclosed. In one aspect, an integrated circuit is metallized by forming an integrated barrier layer structure on a silicon substrate followed by deposition of one or more copper (Cu) layers. The integrated barrier layer structure includes one or more barrier layers selected from tantalum (Ta), tantalum nitride (TaNx), tungsten (W), and tungsten nitride (WNx) conformably deposited on the silicon substrate. After the one or more barrier layers are deposited on the silicon substrate, the silicon substrate is heated to form a silicide layer at the interface between the silicon substrate and the barrier layers.
    • 公开了一种与集成电路制造用铜(Cu)金属化方案兼容的集成阻挡层结构的形成方法。 在一个方面中,通过在硅衬底上形成集成的阻挡层结构,然后沉积一个或多个铜(Cu)层,从而对集成电路进行金属化。 集成阻挡层结构包括从硅(Ta),氮化钽(TaNx),钨(W)和钨氮化物(WNx)中选择的一个或多个势垒层,其顺应地沉积在硅衬底上。 在一个或多个阻挡层沉积在硅衬底上之后,硅衬底被加热以在硅衬底和阻挡层之间的界面处形成硅化物层。
    • 5. 发明申请
    • METHOD AND APPARATUS FOR FORMING IMPROVED METAL INTERCONNECTS
    • 用于形成改进的金属互连的方法和设备
    • WO0007236A3
    • 2000-06-22
    • PCT/US9916887
    • 1999-07-26
    • APPLIED MATERIALS INC
    • HASHIM IMRANCHIANG TONYCHIN BARRY
    • H01L21/285H01L21/28H01L21/768H01L23/522H01L23/532
    • H01L21/76844H01L21/76805H01L21/76814H01L21/76831H01L21/76834H01L21/76838H01L21/76877H01L23/5226H01L23/53238H01L2924/0002H01L2924/00
    • Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter-etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.
    • 公开了形成没有通孔到通孔泄漏电流并具有低电阻的铜互连的方法。 在第一方面中,在氧化铜溅射蚀刻之前在第一金属层上沉积阻挡层以防止铜原子到达层间电介质并在其中形成通孔到通孔漏电流路径。 在第二方面中,在溅射蚀刻之前,在第一金属层上沉积覆盖电介质阻挡层。 在溅射蚀刻期间,覆盖电介质阻挡层重新分布在层间电介质的侧壁上,防止溅射蚀刻的铜原子到达层间电介质并在其中形成通孔到通孔泄漏路径。 在第三方面中,在溅射蚀刻之前,在第一金属层上沉积覆盖电介质阻挡层和阻挡层以防止在溅射蚀刻期间产生的铜原子到达层间电介质并形成通孔到通孔泄漏路径 在其中。