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11. 发明申请

WO2012045509A1 3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY 审中-公开
标题翻译：具有改进可靠性的浮动导电板的3D VIA电容器
公开(公告)号：WO2012045509A1
公开(公告)日：2012-04-12
申请号：PCT/EP2011/064079
申请日：2011-08-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHEN, Fen , YANG, Chih-Chao , LI, Baozhen
发明人： CHEN, Fen , YANG, Chih-Chao , LI, Baozhen
IPC分类号： H01L21/02 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5223 , H01L21/76805 , H01L25/0657 , H01L28/91 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer (110) on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode (118a, b) overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer (120) overlies the first electrode. A first conductive plate (122) is over the first high-k dielectric material layer. A second high-k dielectric material layer (126) overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode (128) is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.
摘要翻译：本发明提供一种3D通孔电容器及其形成方法。电容器包括在衬底上的绝缘层（110）。绝缘层具有通孔，其具有侧壁和底部。第一电极（118a，b）覆盖通孔的侧壁和底部的至少一部分。第一高k电介质材料层（120）覆盖在第一电极上。第一导电板（122）在第一高k电介质材料层之上。第二高k介电材料层（126）覆盖在第一导电板上并留下未填充的通孔的剩余部分。在通孔的剩余部分中形成第二电极（128）。第一导电板基本上平行于第一电极并且不与第一和第二电极接触。还提供了这种3D通孔电容器的阵列。

12. 发明申请

WO2012010479A1 METHOD AND STRUCTURE TO IMPROVE THE CONDUCTIVITY OF NARROW COPPER FILLED VIAS 审中-公开
标题翻译：提高纳米铜填充电导率的方法与结构
公开(公告)号：WO2012010479A1
公开(公告)日：2012-01-26
申请号：PCT/EP2011/061959
申请日：2011-07-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , MCFEELY, Fenton, Read , YANG, Chih-Chao
发明人： MCFEELY, Fenton, Read , YANG, Chih-Chao
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H05K1/09 , H01L21/76846 , H01L21/76864 , H01L21/76873 , H01L21/76883 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , Y10T29/49126 , Y10T29/49165 , H01L2924/00
摘要： Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.
摘要翻译：提供了提高铜（Cu）填充通孔电导率的技术。一方面，提供了制造填充铜的通孔的方法。该方法包括以下步骤。在电介质中蚀刻通孔。通孔内有一个扩散屏障。薄的钌（Ru）层共形沉积到扩散阻挡层上。在Ru层上沉积薄的种子Cu层。进行第一退火以增加种子Cu层的晶粒尺寸。通孔填充有额外的铜。进行第二次退火以增加附加Cu的晶粒尺寸。

13. 发明申请

WO2011139417A2 STRUCTURE AND METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES HAVING SELF-ALIGNED DIELECTRIC CAPS 审中-公开
标题翻译：具有自对准电介质CAPS的互连结构的结构和方法
公开(公告)号：WO2011139417A2
公开(公告)日：2011-11-10
申请号：PCT/US2011/029127
申请日：2011-03-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HORAK, David, V. , NOGAMI, Takeshi , PONOTH, Shom , YANG, Chih-Chao
发明人： HORAK, David, V. , NOGAMI, Takeshi , PONOTH, Shom , YANG, Chih-Chao
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76805 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.
摘要翻译：提供具有自对准电介质盖的互连结构。在基板上形成至少一个金属化层。电介质盖被选择性地沉积在金属化层上。

14. 发明申请

WO2011037710A3 MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY 审中-公开
标题翻译：模块化三维电容阵列
公开(公告)号：WO2011037710A3
公开(公告)日：2011-03-31
申请号：PCT/US2010/046267
申请日：2010-08-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HSU, Louis, L , OUYANG, Xu , YANG, Chih-Chao
发明人： HSU, Louis, L , OUYANG, Xu , YANG, Chih-Chao
IPC分类号： G11C11/24 , G11C11/34
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电连接电容器的开关装置。开关装置包括感测单元，该感测单元被配置为检测电容器的泄漏水平，使得如果泄漏电流超过预定水平，则开关装置电切断电容器。每个电容器模块可以包括单个电容器板，两个电容器板或两个以上的电容器板。采用泄漏传感器和开关器件来电切断电容器阵列中任何变得泄漏的电容器模块，从而保护电容器阵列免于过多的漏电。

15. 发明申请

WO2006113186A3 INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME 审中-公开
标题翻译：互连结构及其制造方法
公开(公告)号：WO2006113186A3
公开(公告)日：2008-07-24
申请号：PCT/US2006013179
申请日：2006-04-07
申请人： IBM , YANG CHIH-CHAO , CLEVENGER LAWRENCE A , COWLEY ANDREW P , DALTON TIMOTHY J , YOON MEEYOUNG H
发明人： YANG CHIH-CHAO , CLEVENGER LAWRENCE A , COWLEY ANDREW P , DALTON TIMOTHY J , YOON MEEYOUNG H
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.
摘要翻译：一种镶嵌线及其形成方法。该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

16. 发明申请

WO2008051674A2 ELECTRICAL FUSE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：电气保险丝及其制造方法
公开(公告)号：WO2008051674A2
公开(公告)日：2008-05-02
申请号：PCT/US2007/079375
申请日：2007-09-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-Chao , YANG, Haining
发明人： YANG, Chih-Chao , YANG, Haining
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a trench feature in a substrate, depositing fuse material in the trench feature and compressive stress liner material over the fuse material, and patterning the compressive stress liner material.
摘要翻译：半导体保险丝包括熔丝元件和减小熔丝元件的电迁移电阻的压应力衬垫。该方法包括在衬底中形成沟槽特征，在沟槽特征中沉积熔丝材料，并在熔丝材料上压缩应力衬里材料，并图案化压缩应力衬里材料。

17. 发明申请

WO2008045989A2 ENHANCED INTERCONNECT STRUCTURE 审中-公开
标题翻译：增强的互连结构
公开(公告)号：WO2008045989A2
公开(公告)日：2008-04-17
申请号：PCT/US2007/081046
申请日：2007-10-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , YANG, Haining, S. , WONG, Keith, Kwong Hon , FAROOQ, Mukta, G.
发明人： YANG, Chih-chao , YANG, Haining, S. , WONG, Keith, Kwong Hon , FAROOQ, Mukta, G.
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76843 , H01L21/76883 , H01L21/76885 , H01L23/53223 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor interconnect structure with improved mechanical strength at the interface of the capping layer (61), the underlying dielectric layer (12) and the diffusion barrier (31). The interconnect structure has a portion (41) of the diffusion barrier material (31) embedded in the capping material (61). The barrier (31) can be either partially or fully embedded in the capping layer (61).
摘要翻译：本发明提供了一种在覆盖层（61），下面的介电层（12）和扩散阻挡层（31）的界面处具有改善的机械强度的半导体互连结构。互连结构具有嵌入在封盖材料（61）中的扩散阻挡材料（31）的一部分（41）。阻挡层（31）可以部分或完全嵌入覆盖层（61）中。

18. 发明申请

WO2007027813A3 MICRO-CAVITY MEMS DEVICE AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：微孔MEMS器件及其制造方法
公开(公告)号：WO2007027813A3
公开(公告)日：2007-12-06
申请号：PCT/US2006033924
申请日：2006-08-30
申请人： IBM , HSU LOUIS C , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , RADENS CARL J , WONG KEITH KWONG HON , YANG CHIH-CHAO
发明人： HSU LOUIS C , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , RADENS CARL J , WONG KEITH KWONG HON , YANG CHIH-CHAO
IPC分类号： H01P1/10
CPC分类号： H01H50/005 , H01H2050/007 , Y10T29/4902 , Y10T29/49105 , Y10T29/49147
摘要： A MEM switch is described having a free moving element (140) within in micro-cavity (40), and guided by at least one inductive element. The switch consists of an upper inductive coil (170); an optional lower inductive coil (190), each having a metallic core (180,200) preferably made of permalloy; a micro-cavity (40); and a free-moving switching element (140) also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires (M_I M_r) and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When gravity cannot be used, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.
摘要翻译：描述了一种MEM开关，其具有在微腔（40）内的自由移动元件（140），并由至少一个电感元件引导。开关由上部感应线圈（170）组成; 可选的下感应线圈（190），每个具有优选由坡莫合金制成的金属芯（180,200）微腔（40）; 以及也由磁性材料制成的自由移动的开关元件（140）。通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。磁场向上吸引自由移动的磁性元件，使两根开放的导线（M_I M_r）短路，从而闭合开关。当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。当不能使用重力时，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

19. 发明申请

WO2007044305A2 PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT 审中-公开
标题翻译：包括用于障碍物增强的氧/氮过渡区的种植层
公开(公告)号：WO2007044305A2
公开(公告)日：2007-04-19
申请号：PCT/US2006/038475
申请日：2006-10-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YANG, Chih-chao , GAUDET, Simon , LAVOIE, Christian , PONOTH, Shom , SPOONER, Terry, A.
发明人： YANG, Chih-chao , GAUDET, Simon , LAVOIE, Christian , PONOTH, Shom , SPOONER, Terry, A.
IPC分类号： H01L23/58
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76856 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.
摘要翻译：提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。优选地，互连导电材料是Cu或AlCu。在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。

20. 发明申请

WO2013002851A1 LOW-PROFILE LOCAL INTERCONNECT AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：低剖面局部互连及其制作方法
公开(公告)号：WO2013002851A1
公开(公告)日：2013-01-03
申请号：PCT/US2012/028708
申请日：2012-03-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , PONOTH, Shom , HORAK, David, V. , KOBURGER, Charles, W. , YANG, Chih-Chao
发明人： PONOTH, Shom , HORAK, David, V. , KOBURGER, Charles, W. , YANG, Chih-Chao
IPC分类号： H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L21/76895 , H01L21/823475 , H04L45/58 , H04L49/15 , H04L49/45
摘要： Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect- transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.
摘要翻译：本发明的实施例提供一种结构。该结构包括多个场效应晶体管，其具有形成在半导体衬底顶部上的栅极叠层，该栅叠层具有形成在其侧壁上的隔离层; 以及直接形成在半导体衬底的顶部上并将多个场效应晶体管之一的至少一个源极/漏极互连到多个场效应中的另一个的至少一个源极/漏极的一个或多个导电触点 - 晶体管，其中所述一个或多个导电触点是具有低于所述栅极堆叠的高度的高度的低轮廓局部互连的一部分。

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