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11. 发明申请

WO2009006513A1 COARSE/FINE PROGRAM VERIFICATION IN NON-VOLATILE MEMORY USING DIFFERENT REFERENCE LEVELS FOR IMPROVED SENSING 审中-公开
标题翻译：使用不同参考水平的非易失性存储器中的粗略/精细程序验证进行改进的感测
公开(公告)号：WO2009006513A1
公开(公告)日：2009-01-08
申请号：PCT/US2008/068988
申请日：2008-07-02
申请人： SANDISK CORPORATION , LEE, Shih-Chung
发明人： LEE, Shih-Chung
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3454 , G11C11/5621 , G11C16/3459
摘要： Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for their intended state. Large sub-threshold swing factors associated with smaller memory cells can affect the accuracy of sense operations, particularly when sensing at a fine verify level after sensing at a coarse verify level without pre-charging the bit line between the different sensing. Different reference potentials are utilized when sensing at a coarse verify level and a final verify level. The different between the reference potentials can compensate for any discharge of the bit line during the coarse level sensing.
摘要翻译：提供非易失性存储器的粗/精编程，其中存储器单元在达到预定状态的粗略验证电平之前以第一编程速率被编程，并且在达到粗校验电平之后但在达到其预期状态的最终验证级别。与更小的存储器单元相关联的大的次阈值摆幅因子可能影响感测操作的精度，特别是当在粗略的验证电平下感测到精确验证电平之后，而不对不同感测之间的位线进行预充电时。在粗略验证级别和最终验证级别进行感测时，会使用不同的参考电位。参考电位之间的差异可以补偿粗略电平检测期间位线的任何放电。

12. 发明申请

WO2007089370A3 SELF-BOOSTING METHOD FOR FLASH MEMORY CELLS 审中-公开
标题翻译：用于闪存存储器的自增强方法
公开(公告)号：WO2007089370A3
公开(公告)日：2007-12-21
申请号：PCT/US2006062338
申请日：2006-12-19
申请人： SANDISK CORP , HEMINK GERRIT JAN , NAKAO HIRONOBU , LEE SHIH-CHUNG
发明人： HEMINK GERRIT JAN , NAKAO HIRONOBU , LEE SHIH-CHUNG
IPC分类号： G11C16/04 , G11C11/56 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427
摘要： A low voltage (e.g. of the order of or one to three volts) instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a flash device such as a NAND flash device and one or more additional word lines next to such word line to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. Different intermediate boosting voltage (s) (e.g. of the order of five to ten volts) may be applied to one or more of the word lines adjacent to the selected word line (that is the word line programming the selected transistor), where the boosting voltage (s) applied to the word line(s) adjacent to the selected word line are/is different from that or those applied to other unselected word lines.
摘要翻译：代替中间VPASS电压（例如5到10伏数量级）的低电压（例如，一级或一到三伏）被施加到紧邻源极或漏极侧选择栅极的字线零点闪存器件，例如NAND闪存器件，以及在该字线旁边的一个或多个附加字线，以在NAND串的不同单元的编程周期期间减少或防止耦合到字线零的存储器单元的阈值电压偏移。不同的中间升压电压（例如，五到十伏数量级）可以施加到与所选字线相邻的一条或多条字线（即所选择的晶体管的字线编程），其中升压施加到与所选字线相邻的字线的电压与施加到所选字线的字线的电压不同。

13. 发明申请

WO2007089370A2 SELF-BOOSTING METHOD FOR FLASH MEMORY CELLS 审中-公开
标题翻译：用于闪存存储器的自增强方法
公开(公告)号：WO2007089370A2
公开(公告)日：2007-08-09
申请号：PCT/US2006/062338
申请日：2006-12-19
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , NAKAO, Hironobu , LEE, Shih-chung
发明人： HEMINK, Gerrit, Jan , NAKAO, Hironobu , LEE, Shih-chung
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427
摘要： A low voltage (e.g. of the order of or one to three volts) instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a flash device such as a NAND flash device and one or more additional word lines next to such word line to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions. In a modified local self boosting scheme, zero volt or low voltages are applied to two or more word lines on the source side and to two or more word lines on the drain side of the selected word line to reduce band-to-band tunneling and to improve the isolation of the channel areas coupled to the selected word line. Different intermediate boosting voltage(s) (e.g. of the order of five to ten volts) may be applied to one or more of the word lines adjacent to the selected word line (that is the word line programming the selected transistor), where the boosting voltage(s) applied to the word line(s) adjacent to the selected word line are/is different from that or those applied to other unselected word lines.
摘要翻译：代替中间VPASS电压（例如5到10伏数量级）的低电压（例如，一级或一到三伏）被施加到紧邻源极或漏极侧选择栅极的字线零点闪存器件，例如NAND闪存器件，以及在该字线旁边的一个或多个附加字线，以在NAND串的不同单元的编程周期期间减少或防止耦合到字线零的存储器单元的阈值电压偏移。这可以在各种不同的自增强方案中的任何一种中实现，包括擦除区域自增强和局部自增强方案。在修改的擦除区域自增强方案中，将低电压施加到所选字线的源极侧上的两个或更多个字线，以减少带间隧穿并改善两个增强的通道区域之间的隔离。在修改后的局部自增强方案中，将零电压或低电压施加到源极侧的两条或更多条字线和所选择的字线的漏极侧上的两条或多条字线，以减少带间隧穿和以改善耦合到所选字线的通道区域的隔离。不同的中间升压电压（例如，五到十伏数量级）可以施加到与所选字线相邻的一条或多条字线（即所选择的晶体管的字线编程），其中升压施加到与所选字线相邻的字线的电压与施加到所选字线的字线的电压不同。

14. 发明申请

WO2012134842A1 REDUCING NEIGHBOR READ DISTURB 审中-公开
标题翻译：减少邻居阅读障碍
公开(公告)号：WO2012134842A1
公开(公告)日：2012-10-04
申请号：PCT/US2012/029553
申请日：2012-03-16
申请人： SANDISK TECHNOLOGIES, INC. , KHANDELWAL, Anubhav , WAN, Jun , LEE, Shih-Chung , LEE, Dana
发明人： KHANDELWAL, Anubhav , WAN, Jun , LEE, Shih-Chung , LEE, Dana
IPC分类号： G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn-2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.
摘要翻译：公开了以减少读取干扰的方式感测非易失性存储设备的方法和设备。技术用于减少作为所选存储单元的邻居的存储器单元的读取干扰。例如，在NAND串上，当前正在读取的所选存储单元旁边的存储器单元可能受益。在一个实施例中，当读取选定字线WLn上的存储单元时，Vread + Delta被施加到WLn + 2和WLn-2。将Vread + Delta应用于第二相邻字线可以减少对相邻字线WLn + 1上的存储器单元的读取干扰。

15. 发明申请

WO2011133404A1 PROGRAMMING NON-VOLATILE STORAGE INCLUDNG REDUCING IMPACT FROM OTHER MEMORY CELLS 审中-公开
标题翻译：编程非易失性存储包括减少其他记忆细胞的影响
公开(公告)号：WO2011133404A1
公开(公告)日：2011-10-27
申请号：PCT/US2011/032575
申请日：2011-04-14
申请人： SANDISK CORPORATION , DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
发明人： DONG, Yingda , LEE, Shih-Chung , OOWADA, Ken
IPC分类号： G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/3459 , G11C2211/5621 , G11C2211/5622
摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.
摘要翻译：提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。存储单元分为两个或更多个组。在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。在第一触发之前，使用随时间增加的编程信号将第一组存储器单元与第二组存储器单元一起编程。在第一触发之后和在第二触发之前，使用已经响应于第一触发而被大幅度降低的编程信号，将第一组存储器单元与第二组存储器单元分开编程。在第二触发之后，第一组存储器单元与第二组存储器单元一起编程，响应于第二触发而使编程信号升高。在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

16. 发明申请

WO2007112213A2 PROGRAM TIME ADJUSTMENT AS FUNCTION OF PROGRAM VOLTAGE FOR IMPROVED PROGRAMMING SPEED 审中-公开
标题翻译：作为改进编程速度的程序电压功能的程序时间调整
公开(公告)号：WO2007112213A2
公开(公告)日：2007-10-04
申请号：PCT/US2007064064
申请日：2007-03-15
申请人： SANDISK CORP , LEE SHIH-CHUNG , MIWA TORU
发明人： LEE SHIH-CHUNG , MIWA TORU
CPC分类号： G11C16/10
摘要： In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced. For example, programming time period may be increased with an increase in the voltage level of the pump pulse required. This allows the programming time period of the program pulse to be increased to a value that compensates for the increased charge-up time that is required for the higher amplitude program pulses to reach the desired programming voltage.
摘要翻译：在非易失性存储器系统中，分配给编程脉冲的编程时间段被调整为所需的泵浦脉冲的电压电平的函数，使得将电荷存储元件编程到所需阈值所需的泵浦脉冲的总数电压降低。例如，可以随着所需的泵浦脉冲的电压电平的增加而增加编程时间段。这允许将编程脉冲的编程时间段增加到补偿更高幅度编程脉冲达到期望编程电压所需的增加的充电时间的值。

17. 发明申请

WO2008137687A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 审中-公开
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：WO2008137687A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062432
申请日：2008-05-02
申请人： SANDISK CORPORATION , DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
发明人： DONG, Yingda , LUTZE, Jeffrey, W. , LEE, Shih-Chung , HEMINK, Gerrit, Jan , OOWADA, Ken
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

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