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11. 发明申请

WO2008089157A2 COLUMN LEAKAGE COMPENSATION IN A SENSING CIRCUIT 审中-公开
标题翻译：感应电路中的柱泄漏补偿
公开(公告)号：WO2008089157A2
公开(公告)日：2008-07-24
申请号：PCT/US2008051023
申请日：2008-01-14
申请人： ATMEL CORP , BEDARIDA LORENZO , MOSTOLA MARIA , MANFRE DAVIDE , FERRARIO DONATO
发明人： BEDARIDA LORENZO , MOSTOLA MARIA , MANFRE DAVIDE , FERRARIO DONATO
IPC分类号： G11C16/28 , G11C7/06 , G11C29/00
CPC分类号： G11C29/12 , G11C7/062 , G11C7/12 , G11C16/04 , G11C16/26
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.
摘要翻译：感测电路。在一个实施例中，感测电路包括存储电路，其包括吸收第一泄漏电流的第一位线，耦合到存储器电路的补偿装置和耦合到补偿装置的补偿电路。补偿电路包括吸收与第一泄漏电流匹配的第二漏电流的第二位线。补偿装置用于基于第二泄漏电流补偿通过电流的第一泄漏电流。根据本文公开的系统和方法，在确定存储单元的状态时，补偿装置和补偿电路可以防止错误。

12. 发明申请

WO2006033832A3 NEW COMPENSATED METHOD TO IMPLEMENT A HIGH VOLTAGE DISCHARGE PHASE AFTER ERASE PULSE IN A FLASH MEMORY DEVICE 审中-公开
标题翻译：用于在闪速存储器件中擦除脉冲之后实现高电压放电相的新补偿方法
公开(公告)号：WO2006033832A3
公开(公告)日：2007-02-15
申请号：PCT/US2005031830
申请日：2005-09-07
申请人： ATMEL CORP , BEDARIDA LORENZO , BARTOLI SIMONE , ODDONE GIORGIO , MANFRE DAVIDE
发明人： BEDARIDA LORENZO , BARTOLI SIMONE , ODDONE GIORGIO , MANFRE DAVIDE
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译：一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极体积电容器的第一板，以及第二放电电路连接到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示存储器单元的体源节点; 并将公共栅极节点和体源极节点耦合到地，以提供完全放电。注入第一板的电流大约等于从第二板提取的电流。以这种方式，在没有复杂的设计或电压限制器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。因此，放电操作的可靠性显着提高。

13. 发明申请

WO2006044203A2 FLEXIBLE OTP SECTOR PROTECTION ARCHITECTURE FOR FLASH MEMORIES 审中-公开
标题翻译：闪存存储器的灵活OTP部门保护架构
公开(公告)号：WO2006044203A2
公开(公告)日：2006-04-27
申请号：PCT/US2005/035788
申请日：2005-10-04
申请人： ATMEL CORPORATION , REGGIORI, Riccardo, Riva , BEDARIDA, Lorenzo , ODDONE, Georgia , CASER, Fabio, Tassan
发明人： REGGIORI, Riccardo, Riva , BEDARIDA, Lorenzo , ODDONE, Georgia , CASER, Fabio, Tassan
IPC分类号： G11C16/04
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译：公开了一种用于保护具有多个块的存储器不被修改的方法和系统。该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。多个OTP单元的OTP单元对应于多个块的块的一部分。当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止修改块的部分。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。当OTP单元处于第二状态时，块的这一部分是写保护的。

14. 发明申请

WO2006026309A2 SYSTEM AND METHOD FOR PRESERVING AN ERROR MARGIN FOR A NON-VOLATILE MEMORY 审中-公开
标题翻译：用于保存非易失性存储器的错误标志的系统和方法
公开(公告)号：WO2006026309A2
公开(公告)日：2006-03-09
申请号：PCT/US2005/030143
申请日：2005-08-23
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , TASSAN CASER, Fabio , BEDARIDA, Lorenzo , MARSELLA, Mirella
发明人： FRULIO, Massimiliano , TASSAN CASER, Fabio , BEDARIDA, Lorenzo , MARSELLA, Mirella
IPC分类号： G11C5/14
CPC分类号： G11C16/28 , G11C7/062
摘要： A system and method for preserving an error margin for a nonvolatile memory that includes a memory cell, a reference cell coupled to a reference current mirror configured to mirror current through the reference cell. The system comprises a memory current mirror coupled to the memory cell and configured to mirror current through the memory cell. A sense amplifier has a first and a second input. The first input is coupled to the reference current mirror and the second input is coupled to the memory current mirror. The sense amplifier is configured to compare a voltage across the memory cell with a voltage across the reference cell.
摘要翻译：一种用于保持包括存储器单元的非易失性存储器的误差容限的系统和方法，耦合到参考电流镜的参考单元，所述参考电池被配置为镜像通过参考单元的电流。该系统包括耦合到存储器单元并被配置为镜像通过存储器单元的电流的存储器电流镜。读出放大器具有第一和第二输入。第一输入耦合到参考电流镜，第二输入耦合到存储器电流镜。读出放大器被配置为将存储器单元两端的电压与参考单元两端的电压进行比较。

15. 发明申请

WO2008089158A3 COMPENSATED CURRENT OFFSET IN A SENSING CIRCUIT 审中-公开
标题翻译：传感电路中的补偿电流偏移
公开(公告)号：WO2008089158A3
公开(公告)日：2009-12-30
申请号：PCT/US2008051024
申请日：2008-01-14
申请人： ATMEL CORP , BEDARIDA LORENZO , PELLI GABRIELE , BARTOLI SIMONE , CHINOSI MAURO
发明人： BEDARIDA LORENZO , PELLI GABRIELE , BARTOLI SIMONE , CHINOSI MAURO
IPC分类号： G11C7/08
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

16. 发明申请

WO2008089160A2 SENSE ARCHITECTURE 审中-公开
标题翻译：感应体系结构
公开(公告)号：WO2008089160A2
公开(公告)日：2008-07-24
申请号：PCT/US2008/051026
申请日：2008-01-15
申请人： ATMEL CORPORATION , PELLI, Gabriele , BEDARIDA, Lorenzo , BARTOLI, Simone , BOSISIO, Giorgio
发明人： PELLI, Gabriele , BEDARIDA, Lorenzo , BARTOLI, Simone , BOSISIO, Giorgio
IPC分类号： G11C16/28
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译：公开了一种存储系统。在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。存储器系统还包括耦合到第一位线的读出放大器。存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。读出放大器能够消除第一和第二瞬态电流。根据本文公开的系统，可以确定存储器单元的状态而不受瞬态电流的不利影响。

17. 发明申请

WO2008089158A2 COMPENSATED CURRENT OFFSET IN A SENSING CIRCUIT 审中-公开
标题翻译：传感电路中的补偿电流偏移
公开(公告)号：WO2008089158A2
公开(公告)日：2008-07-24
申请号：PCT/US2008/051024
申请日：2008-01-14
申请人： ATMEL CORPORATION , BEDARIDA, Lorenzo , PELLI, Gabriele , BARTOLI, Simone , CHINOSI, Mauro
发明人： BEDARIDA, Lorenzo , PELLI, Gabriele , BARTOLI, Simone , CHINOSI, Mauro
IPC分类号： G11C7/08
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

18. 发明申请

WO2006026309A3 SYSTEM AND METHOD FOR PRESERVING AN ERROR MARGIN FOR A NON-VOLATILE MEMORY 审中-公开
标题翻译：用于保存非易失性存储器的错误标志的系统和方法
公开(公告)号：WO2006026309A3
公开(公告)日：2007-08-16
申请号：PCT/US2005030143
申请日：2005-08-23
申请人： ATMEL CORP , FRULIO MASSIMILIANO , TASSAN CASER FABIO , BEDARIDA LORENZO , MARSELLA MIRELLA
发明人： FRULIO MASSIMILIANO , TASSAN CASER FABIO , BEDARIDA LORENZO , MARSELLA MIRELLA
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/062
摘要： A system and method for preserving an error margin for a nonvolatile memory that includes a memory cell, a reference cell coupled to a reference current mirror configured to mirror current through the reference cell. The system comprises a memory current mirror coupled to the memory cell and configured to mirror current through the memory cell. A sense amplifier has a first and a second input. The first input is coupled to the reference current mirror and the second input is coupled to the memory current mirror. The sense amplifier is configured to compare a voltage across the memory cell with a voltage across the reference cell.
摘要翻译：一种用于保持非易失性存储器的误差容限的系统和方法，所述非易失性存储器包括存储器单元，耦合到参考电流镜的参考单元，所述参考电池被配置为镜像通过所述参考单元的该系统包括耦合到存储器单元并被配置为镜像通过存储器单元的电流的存储器电流镜。读出放大器具有第一和第二输入。第一输入耦合到参考电流镜，第二输入耦合到存储器电流镜。读出放大器被配置为将存储器单元两端的电压与参考单元两端的电压进行比较。

19. 发明申请

WO2004077439A2 AN APPARATUS AN METHOD FOR A CONFIGURABLE MIRROR FAST SENSE AMPLIFIER 审中-公开
标题翻译：一种用于可配置反射镜快速感测放大器的装置
公开(公告)号：WO2004077439A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/004729
申请日：2004-02-17
申请人： ATMEL CORPORATION , BEDARIDA, Lorenzo , SACCO, Andrea , MARZIANI, Monica
发明人： BEDARIDA, Lorenzo , SACCO, Andrea , MARZIANI, Monica
IPC分类号： G11C
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C2207/063 , G11C2207/2254
摘要： A configurable mirror sense amplifier system for flash memory having the following features. A power source generates a reference voltage. A plurality of transistors is biased at the reference voltage. The plurality of transistors is each coupled to a second transistor. Each of the plurality of transistors is also configured to provide a current for comparison with the flash memory. The reference voltage is internal, stable and independent from variations of a power supply or temperature. The plurality of transistors is in parallel with one another. A mirror transistor is coupled to the plurality of transistors. The plurality of transistors is configured so that at least one of at least one transistor is activated with a signal in order to provide the current for comparison to the flash memory. Also, the reference voltage may be modified in order to modify the current for comparison to the flash memory.
摘要翻译：用于闪存的可配置镜像读出放大器系统具有以下特征。电源产生参考电压。多个晶体管偏置在参考电压。多个晶体管各自耦合到第二晶体管。多个晶体管中的每一个还被配置为提供用于与闪存进行比较的电流。参考电压是内部的，稳定的并且与电源或温度的变化无关。多个晶体管彼此并联。镜像晶体管被耦合到多个晶体管。多个晶体管被配置为使得至少一个晶体管中的至少一个晶体管被信号激活以提供用于与闪存进行比较的电流。此外，参考电压可能会修改，以修改电流以与闪存进行比较。

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