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1. 发明申请

WO2006026309A2 SYSTEM AND METHOD FOR PRESERVING AN ERROR MARGIN FOR A NON-VOLATILE MEMORY 审中-公开
标题翻译：用于保存非易失性存储器的错误标志的系统和方法
公开(公告)号：WO2006026309A2
公开(公告)日：2006-03-09
申请号：PCT/US2005/030143
申请日：2005-08-23
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , TASSAN CASER, Fabio , BEDARIDA, Lorenzo , MARSELLA, Mirella
发明人： FRULIO, Massimiliano , TASSAN CASER, Fabio , BEDARIDA, Lorenzo , MARSELLA, Mirella
IPC分类号： G11C5/14
CPC分类号： G11C16/28 , G11C7/062
摘要： A system and method for preserving an error margin for a nonvolatile memory that includes a memory cell, a reference cell coupled to a reference current mirror configured to mirror current through the reference cell. The system comprises a memory current mirror coupled to the memory cell and configured to mirror current through the memory cell. A sense amplifier has a first and a second input. The first input is coupled to the reference current mirror and the second input is coupled to the memory current mirror. The sense amplifier is configured to compare a voltage across the memory cell with a voltage across the reference cell.
摘要翻译：一种用于保持包括存储器单元的非易失性存储器的误差容限的系统和方法，耦合到参考电流镜的参考单元，所述参考电池被配置为镜像通过参考单元的电流。该系统包括耦合到存储器单元并被配置为镜像通过存储器单元的电流的存储器电流镜。读出放大器具有第一和第二输入。第一输入耦合到参考电流镜，第二输入耦合到存储器电流镜。读出放大器被配置为将存储器单元两端的电压与参考单元两端的电压进行比较。

2. 发明申请

WO2008115570A1 NAN FLASH MEMORY WITH HIERARCHICAL BITLINE AND WORDLINE ARCHITECTURE 审中-公开
标题翻译：具有分层位线和WORDLINE架构的NAN FLASH存储器
公开(公告)号：WO2008115570A1
公开(公告)日：2008-09-25
申请号：PCT/US2008/003716
申请日：2008-03-20
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , BEDARIDA, Lorenzo , BARTOLI, Simone , TASSAN CASER, Fabio
发明人： FRULIO, Massimiliano , BEDARIDA, Lorenzo , BARTOLI, Simone , TASSAN CASER, Fabio
IPC分类号： G11C16/04 , G11C16/08
CPC分类号： G11C16/08 , G11C5/025 , G11C5/063
摘要： Some embodiments of the apparatus relate to NAND-like memory arrays employing high- density NOR-like memory devices. A flash memory integrated circuit includes a plurality of flash memory arrays. A global wordline driver is associated with each array, each global wordline driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bitlines. A plurality of sub-arrays in each array each include a plurality of NAND flash memory cells coupled to local wordlines and local bitlines. A local wordline driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local wordlines in its sub-array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bitline driver is coupled between selected ones of the local bitlines in each sub-array and selected ones of the plurality of bitlines.
摘要翻译：该装置的一些实施例涉及采用高密度NOR样存储器件的类NAND存储器阵列。闪存集成电路包括多个闪存阵列。全局字线驱动器与每个阵列相关联，每个全局字线驱动器耦合到多个选择线。多个读出放大器分别耦合到多个位线。每个阵列中的多个子阵列各自包括耦合到本地字线和本地位线的多个NAND快闪存储器单元。本地字线驱动器与每个子阵列相关联并且耦合到多个选择线并且被配置为驱动与其子阵列中的多个NAND快闪存储器单元中的选定的一个相关联的其子阵列中的本地字线中的一个。局部位线驱动器耦合在每个子阵列中的本地位线的选定的位线和多个位线中的选定的位线之间。

3. 发明申请

WO2008073862A2 CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS 审中-公开
标题翻译：用于产生多个输出电压的充电泵
公开(公告)号：WO2008073862A2
公开(公告)日：2008-06-19
申请号：PCT/US2007/086912
申请日：2007-12-10
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , SIVERO, Stefano , PASSERINI, Marco , TASSAN, Caser, Fabio
发明人： FRULIO, Massimiliano , SIVERO, Stefano , PASSERINI, Marco , TASSAN, Caser, Fabio
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/007 , H02M2001/009
摘要： A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.
摘要翻译：用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联电荷泵级，第一组中的第一电荷泵级的输入从电源电压驱动。第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。提供了第二组级联电荷泵级，第二组的第一电荷泵级的输入从第一组的最后一个电荷泵级的输出驱动。第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

4. 发明申请

WO2008089159A2 SENSE AMPLIFIER WITH STAGES TO REDUCE CAPACITANCE MISMATCH IN CURRENT MIRROR LOAD 审中-公开
标题翻译：具有降低电流误差的步骤的感应放大器
公开(公告)号：WO2008089159A2
公开(公告)日：2008-07-24
申请号：PCT/US2008/051025
申请日：2008-01-15
申请人： ATMEL CORPORATION , PELLI, Gabriele , BEDARIDA, Lorenzo , FRULIO, Massimiliano , MANFRE', Davide
发明人： PELLI, Gabriele , BEDARIDA, Lorenzo , FRULIO, Massimiliano , MANFRE', Davide
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

5. 发明申请

WO2008124095A1 SERIAL INTERFACE MEMORY TESTING APPARATUS AND METHOD 审中-公开
标题翻译：串行接口存储器测试装置和方法
公开(公告)号：WO2008124095A1
公开(公告)日：2008-10-16
申请号：PCT/US2008/004447
申请日：2008-04-04
申请人： ATMEL CORPORATION , SURICO, Stefano , PASSERINI, Marco , FRULIO, Massimiliano , POJER, Alex
发明人： SURICO, Stefano , PASSERINI, Marco , FRULIO, Massimiliano , POJER, Alex
IPC分类号： G11C29/00 , G11C29/32
CPC分类号： G11C29/32 , G11C29/003 , G11C29/1201
摘要： The apparatus, systems and methods described herein relate to a serial-interface flash memory device (10) including a first terminal (12) to receive input data in a first operating phase and to receive a synchronization signal in a test operating phase, a second terminal (20) to receive a clock input in the first operating phase and a test level signal in a test operating phase, and a logic circuit (16) to recognize input data commands indicating that a test operating phase is to commence and to inhibit the clock input during the test operation phase. Other apparatus embodiments and embodiments of methods of operating the apparatus are disclosed.
摘要翻译：本文所述的装置，系统和方法涉及串行接口闪存设备（10），其包括在第一操作阶段接收输入数据并在测试操作阶段接收同步信号的第一终端（12），第二终端端子（20），用于接收第一工作阶段的时钟输入和测试工作阶段的测试电平信号;以及逻辑电路（16），用于识别表示测试工作阶段要开始的输入数据命令，并且禁止在测试操作阶段的时钟输入。公开了操作该装置的方法的其它装置实施例和实施例。

6. 发明申请

WO2006044163A2 SYSTEM AND METHOD FOR AVOIDING OFFSET IN AND REDUCING THE FOOTPRINT OF A NON-VOLATILE MEMORY 审中-公开
标题翻译：避免偏差和减少非易失性存储器容量的系统和方法
公开(公告)号：WO2006044163A2
公开(公告)日：2006-04-27
申请号：PCT/US2005/035166
申请日：2005-10-03
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , RIVA REGGIORI, Riccardo , SACCO, Andrea , FIGINI, Luca
发明人： FRULIO, Massimiliano , RIVA REGGIORI, Riccardo , SACCO, Andrea , FIGINI, Luca
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.
摘要翻译：一种用于避免偏移并减小具有多个存储器组电路的非易失性存储器的占位面积的系统和方法。每个存储体电路具有耦合到读出放大器，耦合到存储器单元的行和列解码器以及耦合到读出放大器的偏置电路的存储单元。该系统包括耦合到多个存储体电路中的每一个的参考单元矩阵。参考单元矩阵被配置为为多个存储体电路中的每一个提供参考单元电流。

7. 发明申请

WO2006044942A3 METHOD AND SYSTEM FOR PROVIDING SENSING CIRCUITRY IN A MULTI-BANK MEMORY DEVICE 审中-公开
公开(公告)号：WO2006044942A3
公开(公告)日：2006-04-27
申请号：PCT/US2005/037546
申请日：2005-10-18
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , SIVERO, Stefano , CASER, Fabio, Tassan , CHINOSI, Mauro
发明人： FRULIO, Massimiliano , SIVERO, Stefano , CASER, Fabio, Tassan , CHINOSI, Mauro
IPC分类号： G11C8/00
摘要： A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.

8. 发明申请

WO2008076546A2 METHOD AND DEVICE FOR MANAGING A POWER SUPPLY POWER-ON SEQUENCE 审中-公开
标题翻译：用于管理电源供电序列的方法和设备
公开(公告)号：WO2008076546A2
公开(公告)日：2008-06-26
申请号：PCT/US2007/084166
申请日：2007-11-08
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , SURICO, Stefano , BETTINI, Andrea , MARZIANI, Monica
发明人： FRULIO, Massimiliano , SURICO, Stefano , BETTINI, Andrea , MARZIANI, Monica
IPC分类号： H03L7/00
CPC分类号： G11C5/147 , G11C5/143
摘要： Many circuits require a minimum voltage supply level before proper operation may be initiated. Power-on control circuits have typically used a voltage supply level detector and have compared that level with an internal reference. The internal reference typically has a dependence on device threshold, accuracy of tracking electrical characteristics in the device, as well as temperature and processing variation. The present invention (400) incorporates a typical supply voltage detector (410) to trigger a reference voltage generator (420). The reference voltage generator (420) is a temperature and process independent supply capable of operating at low power supply levels. An output voltage level from the reference voltage generator (420) is compared with the ramping-up supply voltage. When the ramping-up supply voltage is greater than the reference voltage generator output voltage level an enable signal is produced. The enable signal signifies to system circuitry that a supply voltage level great enough to support nominal operations is present.
摘要翻译：许多电路需要最小电压供应水平才能启动适当的操作。上电控制电路通常使用电压电平检测器，并将该电平与内部参考值进行比较。内部参考通常依赖于器件阈值，器件跟踪电气特性的精度以及温度和处理变化。本发明（400）包括用于触发参考电压发生器（420）的典型电源电压检测器（410）。参考电压发生器（420）是能够以低电源电平工作的温度和处理独立电源。将来自参考电压发生器（420）的输出电压电平与升高电源电压进行比较。当升高电源电压大于参考电压发生器输出电压电平时，产生使能信号。使能信号表示系统电路，电源电压水平足以支持标称操作。

9. 发明申请

WO2008057835A2 LOW VOLTAGE COLUMN DECODER SHARING A MEMORY ARRAY P-WELL 审中-公开
标题翻译：低电压柱解码器共享存储阵列P-WELL
公开(公告)号：WO2008057835A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/082875
申请日：2007-10-29
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , SURICO, Stefano , SACCO, Andrea , MANFRE, Davide
发明人： FRULIO, Massimiliano , SURICO, Stefano , SACCO, Andrea , MANFRE, Davide
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/08
摘要： A plurality of memory sub-arrays (302A - 302X) are formed in a p-well region (304). Each of the memory sub-arrays (302A - 302X) has at least one first-level column decoder (306A - 306X) that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder (316) is formed outside of the p-well region (304) and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers (320). During a memory erase mode of operation, a high voltage is provided to bias the p-well region (304) and a plurality of high-voltage switches (326A - 326X) are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders (306A - 306X). One or more intermediate-level column decoders (312) are formed as low-voltage selector transistors in the p-well (304) between the first-level column decoder (306A - 306X) and the last-level column decoder (316). Each of the intermediate- level column decoders (312) also has a high-voltage switch (326Y) that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate- level column decoders (312).
摘要翻译：多个存储器子阵列（302A-302X）形成在p阱区域（304）中。每个存储子阵列（302A-302X）具有至少一个第一级解码器（306A-306X），其包括也形成在p阱内的多个低压MOS选择晶体管。最后一级解码器（316）形成在p阱区域（304）的外部，并且包括高压MOS晶体管，以向读出放大器（320）阵列之一提供输出信号。在存储器擦除操作模式期间，提供高电压以偏置p阱区域（304），并且激活多个高压开关（326A-326X）以向选择器晶体管的栅极端提供高电压在第一级列解码器（306A-306X）中。在第一级列解码器（306A-306X）和最后级列解码器（316）之间的p阱（304）中形成一个或多个中间级列解码器（312）作为低电压选择晶体管。每个中间级列解码器（312）还具有在存储器擦除操作模式期间被激活以向中间级列解码器（312）的栅极端提供高电压的高压开关（326Y）。

10. 发明申请

WO2006058134A3 METHOD AND SYSTEM FOR REGULATING A PROGRAM VOLTAGE VALUE DURING MULTILEVEL MEMORY DEVICE PROGRAMMING 审中-公开
公开(公告)号：WO2006058134A3
公开(公告)日：2006-06-01
申请号：PCT/US2005/042570
申请日：2005-11-23
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , BARTOLI, Simone , MANFRÉ, David , SACCO, Andrea
发明人： FRULIO, Massimiliano , BARTOLI, Simone , MANFRÉ, David , SACCO, Andrea
IPC分类号： G11C16/04
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.

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