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1. 发明申请

WO2008089159A2 SENSE AMPLIFIER WITH STAGES TO REDUCE CAPACITANCE MISMATCH IN CURRENT MIRROR LOAD 审中-公开
标题翻译：具有降低电流误差的步骤的感应放大器
公开(公告)号：WO2008089159A2
公开(公告)日：2008-07-24
申请号：PCT/US2008/051025
申请日：2008-01-15
申请人： ATMEL CORPORATION , PELLI, Gabriele , BEDARIDA, Lorenzo , FRULIO, Massimiliano , MANFRE', Davide
发明人： PELLI, Gabriele , BEDARIDA, Lorenzo , FRULIO, Massimiliano , MANFRE', Davide
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

2. 发明申请

WO2006033832A2 NEW COMPENSATED METHOD TO IMPLEMENT A HIGH VOLTAGE DISCHARGE PHASE AFTER ERASE PULSE IN A FLASH MEMORY DEVICE 审中-公开
标题翻译：用于在闪存存储器件中擦除脉冲之后实现高电压放电相位的新补偿方法
公开(公告)号：WO2006033832A2
公开(公告)日：2006-03-30
申请号：PCT/US2005/031830
申请日：2005-09-07
申请人： ATMEL CORPORATION , BEDARIDA, Lorenzo , BARTOLI, Simone , ODDONE, Giorgio , MANFRÉ, Davide
发明人： BEDARIDA, Lorenzo , BARTOLI, Simone , ODDONE, Giorgio , MANFRÉ, Davide
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译：一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极 - 体积电容器的第一板，以及将第二放电电路耦合到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示存储单元的批量源节点; 并将公共栅极节点和体源节点耦合到地以提供完全放电。注入第一板的电流大约等于从第二板提取的电流。以这种方式，在没有复杂设计或限压器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。因此，放电操作的可靠性显着提高。

3. 发明申请

WO2008089160A3 SENSE ARCHITECTURE 审中-公开
公开(公告)号：WO2008089160A3
公开(公告)日：2008-09-25
申请号：PCT/US2008051026
申请日：2008-01-15
申请人： ATMEL CORP , PELLI GABRIELE , BEDARIDA LORENZO , BARTOLI SIMONE , BOSISIO GIORGIO
发明人： PELLI GABRIELE , BEDARIDA LORENZO , BARTOLI SIMONE , BOSISIO GIORGIO
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译：存储系统被公开。在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。存储器系统还包括耦合到第一位线的读出放大器。存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。读出放大器使第一和第二瞬态电流被消除。根据这里公开的系统，可以确定存储单元的状态而不受瞬态电流的不利影响。

4. 发明申请

WO2004077439A3 AN APPARATUS AN METHOD FOR A CONFIGURABLE MIRROR FAST SENSE AMPLIFIER 审中-公开
标题翻译：一种可配置的镜像快速感测放大器的方法
公开(公告)号：WO2004077439A3
公开(公告)日：2004-12-29
申请号：PCT/US2004004729
申请日：2004-02-17
申请人： ATMEL CORP , BEDARIDA LORENZO , SACCO ANDREA , MARZIANI MONICA
发明人： BEDARIDA LORENZO , SACCO ANDREA , MARZIANI MONICA
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G11C11/34
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C2207/063 , G11C2207/2254
摘要： A configurable mirror sense amplifier system for flash memory having the following features. A power source generates a reference voltage. A plurality of transistors is biased at the reference voltage. The plurality of transistors is each coupled to a second transistor. Each of the plurality of transistors is also configured to provide a current for comparison with the flash memory. The reference voltage is internal, stable and independent from variations of a power supply or temperature. The plurality of transistors is in parallel with one another. A mirror transistor is coupled to the plurality of transistors. The plurality of transistors is configured so that at least one of at least one transistor is activated with a signal in order to provide the current for comparison to the flash memory. Also, the reference voltage may be modified in order to modify the current for comparison to the flash memory.
摘要翻译：一种用于闪存的可配置的镜像放大器系统，具有以下特征。电源产生参考电压。多个晶体管被偏置在参考电压。多个晶体管各自耦合到第二晶体管。多个晶体管中的每一个也被配置为提供用于与闪速存储器进行比较的电流。参考电压是内部的，稳定的，独立于电源或温度的变化。多个晶体管彼此并联。反射镜晶体管耦合到多个晶体管。多个晶体管被配置为使得至少一个晶体管中的至少一个被激活，以便提供用于与闪存相比较的电流。此外，可以修改参考电压以便修改用于与闪存存储器进行比较的电流。

5. 发明申请

WO2006135658A3 SYSTEM AND METHOD FOR MATCHING RESISTANCE IN A NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：WO2006135658A3
公开(公告)日：2009-04-23
申请号：PCT/US2006022220
申请日：2006-06-07
申请人： ATMEL CORP , BEDARIDA LORENZO , SACCO ANDREA , ODDONE GIORGIO , BARTOLI SIMONE
发明人： BEDARIDA LORENZO , SACCO ANDREA , ODDONE GIORGIO , BARTOLI SIMONE
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

6. 发明申请

WO2008089157A3 COLUMN LEAKAGE COMPENSATION IN A SENSING CIRCUIT 审中-公开
公开(公告)号：WO2008089157A3
公开(公告)日：2008-07-24
申请号：PCT/US2008/051023
申请日：2008-01-14
申请人： ATMEL CORPORATION , BEDARIDA, Lorenzo , MOSTOLA, Maria , MANFRE', Davide , FERRARIO, Donato
发明人： BEDARIDA, Lorenzo , MOSTOLA, Maria , MANFRE', Davide , FERRARIO, Donato
IPC分类号： G11C16/28 , G11C7/06 , G11C29/00
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.

7. 发明申请

WO2006135658A2 SYSTEM AND METHOD FOR MATCHING RESISTANCE IN A NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：WO2006135658A2
公开(公告)日：2006-12-21
申请号：PCT/US2006/022220
申请日：2006-06-07
申请人： ATMEL CORPORATION , BEDARIDA, Lorenzo , SACCO, Andrea , ODDONE, Giorgio , BARTOLI, Simone
发明人： BEDARIDA, Lorenzo , SACCO, Andrea , ODDONE, Giorgio , BARTOLI, Simone
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

8. 发明申请

WO2006044203A3 FLEXIBLE OTP SECTOR PROTECTION ARCHITECTURE FOR FLASH MEMORIES 审中-公开
标题翻译：闪存存储器的灵活OTP部门保护架构
公开(公告)号：WO2006044203A3
公开(公告)日：2006-11-09
申请号：PCT/US2005035788
申请日：2005-10-04
申请人： ATMEL CORP , REGGIORI RICCARDO RIVA , BEDARIDA LORENZO , ODDONE GEORGIA , CASER FABIO TASSAN
发明人： REGGIORI RICCARDO RIVA , BEDARIDA LORENZO , ODDONE GEORGIA , CASER FABIO TASSAN
IPC分类号： G11C17/00
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks (132, 134, 136, 138) from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells (122, 124, 126, 128) and OTP cell logic (110) coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译：公开了一种用于保护具有多个块（132,134,136,138）的存储器的方法和系统。该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元（122,124,126,128）和OTP单元逻辑（110）。多个OTP单元的OTP单元对应于多个块的块的一部分。当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止修改块的部分。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。当OTP单元处于第二状态时，块的这一部分是写保护的。

9. 发明申请

WO2008089159A3 SENSE AMPLIFIER WITH STAGES TO REDUCE CAPACITANCE MISMATCH IN CURRENT MIRROR LOAD 审中-公开
标题翻译：具有降低电流误差的步骤的感应放大器
公开(公告)号：WO2008089159A3
公开(公告)日：2009-12-30
申请号：PCT/US2008051025
申请日：2008-01-15
申请人： ATMEL CORP , PELLI GABRIELE , BEDARIDA LORENZO , FRULIO MASSIMILIANO , MANFRE DAVIDE
发明人： PELLI GABRIELE , BEDARIDA LORENZO , FRULIO MASSIMILIANO , MANFRE DAVIDE
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

10. 发明申请

WO2008115570A1 NAN FLASH MEMORY WITH HIERARCHICAL BITLINE AND WORDLINE ARCHITECTURE 审中-公开
标题翻译：具有分层位线和WORDLINE架构的NAN FLASH存储器
公开(公告)号：WO2008115570A1
公开(公告)日：2008-09-25
申请号：PCT/US2008/003716
申请日：2008-03-20
申请人： ATMEL CORPORATION , FRULIO, Massimiliano , BEDARIDA, Lorenzo , BARTOLI, Simone , TASSAN CASER, Fabio
发明人： FRULIO, Massimiliano , BEDARIDA, Lorenzo , BARTOLI, Simone , TASSAN CASER, Fabio
IPC分类号： G11C16/04 , G11C16/08
CPC分类号： G11C16/08 , G11C5/025 , G11C5/063
摘要： Some embodiments of the apparatus relate to NAND-like memory arrays employing high- density NOR-like memory devices. A flash memory integrated circuit includes a plurality of flash memory arrays. A global wordline driver is associated with each array, each global wordline driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bitlines. A plurality of sub-arrays in each array each include a plurality of NAND flash memory cells coupled to local wordlines and local bitlines. A local wordline driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local wordlines in its sub-array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bitline driver is coupled between selected ones of the local bitlines in each sub-array and selected ones of the plurality of bitlines.
摘要翻译：该装置的一些实施例涉及采用高密度NOR样存储器件的类NAND存储器阵列。闪存集成电路包括多个闪存阵列。全局字线驱动器与每个阵列相关联，每个全局字线驱动器耦合到多个选择线。多个读出放大器分别耦合到多个位线。每个阵列中的多个子阵列各自包括耦合到本地字线和本地位线的多个NAND快闪存储器单元。本地字线驱动器与每个子阵列相关联并且耦合到多个选择线并且被配置为驱动与其子阵列中的多个NAND快闪存储器单元中的选定的一个相关联的其子阵列中的本地字线中的一个。局部位线驱动器耦合在每个子阵列中的本地位线的选定的位线和多个位线中的选定的位线之间。

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