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91. 发明申请

WO2006052929A1 ADAPTIVE MEMORY CALIBRATION USING BINS 审中-公开
标题翻译：使用BINS的自适应内存校准
公开(公告)号：WO2006052929A1
公开(公告)日：2006-05-18
申请号：PCT/US2005/040363
申请日：2005-11-07
申请人： QUALCOMM INCORPORATED , PATEL, Jagrut Viliskumar , BULLARD, Gregory , KAPOOR, Sanat
发明人： PATEL, Jagrut Viliskumar , BULLARD, Gregory , KAPOOR, Sanat
IPC分类号： G01R31/3193 , G11C29/50
CPC分类号： G11C7/22 , G01R31/3193 , G01R31/31937 , G11C7/04 , G11C7/222 , G11C11/401 , G11C29/022 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2254
摘要： An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.
摘要翻译：电子设备包括电子部件和集成电路，其中集成电路被配置为产生系统时钟和具有来自系统时钟的可编程延迟的外部时钟，将外部时钟提供给电子部件，确定电子部件之间的延迟范围系统时钟和集成电路和电子部件可以通信的外部时钟，并且基于延迟范围以多个预定延迟值中的一个对外部时钟进行编程。

92. 发明申请

WO2005104132A1 ELECTRONIC CIRCUIT WITH MEMORY FOR WHICH A THRESHOLD LEVEL IS SELECTED 审中-公开
标题翻译：具有选择阈值级别的存储器的电子电路
公开(公告)号：WO2005104132A1
公开(公告)日：2005-11-03
申请号：PCT/IB2005/051305
申请日：2005-04-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , MARSMAN, Albert, W , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J. , STEK, Aalbert , BOEVE, Hans, M., B.. , PHILLIPS, Gavin, N.
发明人： VAN ACHT, Victor, M., G. , MARSMAN, Albert, W , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J. , STEK, Aalbert , BOEVE, Hans, M., B.. , PHILLIPS, Gavin, N.
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C7/1006 , G11C2207/104 , G11C2207/2254 , G11C2211/5634
摘要： A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.
摘要翻译：存储器（10）被组织为存储单元电路（100）的矩阵行和列，并且包括耦合到存储器单元（100）的行的位线导体（12）。感测电路（14）耦合到位线导体（12）。感测电路（14）被布置成通过将来自多个位线导体（12）的相应信号与位线导体（12）共用的基准电平进行比较来形成相应的数据信号。具有耦合到多个位线导体（12）的输入的参考电平选择电路（16）被布置成控制参考电平。参考电平选择电路（16）根据多个位线导体（12）上的相应模拟信号电平选择参考电平，使得来自多个位线导体（12）中的至少相应的模拟信号电平，位于参考水平的相应侧。

93. 发明申请

WO2005072329A2 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 审中-公开
标题翻译：通信通道校准条件
公开(公告)号：WO2005072329A2
公开(公告)日：2005-08-11
申请号：PCT/US2005002301
申请日：2005-01-25
申请人： RAMBUS INC , WARE FREDERICK A , PEREGO RICHARD E , HAMPEL CRAIG E
发明人： WARE FREDERICK A , PEREGO RICHARD E , HAMPEL CRAIG E
IPC分类号： H04B1/38 , H04L1/24 , H04L7/10 , H04L27/00
CPC分类号： H04L1/242 , G11C7/04 , G11C7/1057 , G11C7/1084 , G11C29/022 , G11C29/025 , G11C29/028 , G11C2207/2254 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12 , H04L27/00
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
摘要翻译：方法和系统提供在通信信道的正常操作期间不时地执行校准周期。校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。使用第二组件上的接收器从通信链路接收校准模式。响应于所接收的校准模式来确定通信信道的参数的校准值。校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

94. 发明申请

WO2005038813A3 METHOD AND DEVICE FOR OPERATING ELECTRONIC SEMICONDUCTOR COMPONENTS VIA SIGNAL LINES 审中-公开
标题翻译：通过信号线操作电子半导体元件的方法和装置
公开(公告)号：WO2005038813A3
公开(公告)日：2005-06-16
申请号：PCT/EP2004010003
申请日：2004-09-08
申请人： INFINEON TECHNOLOGIES AG , DICKMAN RORY
发明人： DICKMAN RORY
IPC分类号： G06F11/24 , G06F13/16 , G11C7/10
CPC分类号： G06F11/24 , G11C7/10 , G11C2207/2254
摘要： The invention relates to a method for operating electronic semiconductor components via signal lines, particularly memory components, whereby the semiconductor components are arranged in groups to form modules, and the modules are connected to the signal lines. The inventive method comprises the following steps: determining and evaluating a signal quality on the signal lines of the semiconductor components of the modules during a signal transmission by using predetermined electrical criteria; selecting semiconductor components, and; using the selected semiconductor components according to a result of the evaluation.
摘要翻译：本发明涉及一种方法，用于经由信号线电子半导体器件的操作，在特定的存储器芯片，其中半导体块被排列在模块组，并且所述模块被连接到所述信号线，所述方法包括以下步骤：确定和评估的所述半导体元件的信号线的信号质量基于预定的电准则进行信号传输期间的模块，选择半导体器件以及根据评估结果使用所选择的半导体器件。

95. 发明申请

WO2005050842A2 APPARATUS AND METHOD FOR GENERATING A DELAYED CLOCK SIGNAL 审中-公开
标题翻译：用于产生延迟时钟信号的装置和方法
公开(公告)号：WO2005050842A2
公开(公告)日：2005-06-02
申请号：PCT/US2004037503
申请日：2004-11-08
申请人： MICRON TECHNOLOGY INC , JANZEN LEEL S
发明人： JANZEN LEEL S
IPC分类号： G06F1/04 , G11C7/10 , H03K
CPC分类号： G11C7/1066 , G06F1/04 , G06F1/10 , G06F1/12 , G11C7/1072 , G11C7/222 , G11C2207/2254
摘要： An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.
摘要翻译：提供了一种用于产生延迟时钟信号的装置和方法。时钟信号发生器包括用于从输入时钟信号产生输出时钟信号的同步电路，并且还包括具有耦合到同步电路的输出的输入的延迟电路。延迟电路根据根据选择信号选择的多个可编程时间延迟中的一个提供相对于来自同步电路的时钟信号具有延迟的输出时钟信号。产生时钟信号的方法包括将内部时钟信号与外部时钟信号同步，并且基于指示外部时钟频率的选择值来延迟内部时钟信号的不同量以提供时钟信号。

96. 发明申请

WO2004077439A3 AN APPARATUS AN METHOD FOR A CONFIGURABLE MIRROR FAST SENSE AMPLIFIER 审中-公开
标题翻译：一种可配置的镜像快速感测放大器的方法
公开(公告)号：WO2004077439A3
公开(公告)日：2004-12-29
申请号：PCT/US2004004729
申请日：2004-02-17
申请人： ATMEL CORP , BEDARIDA LORENZO , SACCO ANDREA , MARZIANI MONICA
发明人： BEDARIDA LORENZO , SACCO ANDREA , MARZIANI MONICA
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G11C11/34
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C2207/063 , G11C2207/2254
摘要： A configurable mirror sense amplifier system for flash memory having the following features. A power source generates a reference voltage. A plurality of transistors is biased at the reference voltage. The plurality of transistors is each coupled to a second transistor. Each of the plurality of transistors is also configured to provide a current for comparison with the flash memory. The reference voltage is internal, stable and independent from variations of a power supply or temperature. The plurality of transistors is in parallel with one another. A mirror transistor is coupled to the plurality of transistors. The plurality of transistors is configured so that at least one of at least one transistor is activated with a signal in order to provide the current for comparison to the flash memory. Also, the reference voltage may be modified in order to modify the current for comparison to the flash memory.
摘要翻译：一种用于闪存的可配置的镜像放大器系统，具有以下特征。电源产生参考电压。多个晶体管被偏置在参考电压。多个晶体管各自耦合到第二晶体管。多个晶体管中的每一个也被配置为提供用于与闪速存储器进行比较的电流。参考电压是内部的，稳定的，独立于电源或温度的变化。多个晶体管彼此并联。反射镜晶体管耦合到多个晶体管。多个晶体管被配置为使得至少一个晶体管中的至少一个被激活，以便提供用于与闪存相比较的电流。此外，可以修改参考电压以便修改用于与闪存存储器进行比较的电流。

97. 发明申请

WO2004042917A3 SENSE AMPLIFIER THERMAL CORRECTION SCHEME 审中-公开
标题翻译：感应放大器热修正方案
公开(公告)号：WO2004042917A3
公开(公告)日：2004-09-16
申请号：PCT/US0334302
申请日：2003-10-29
申请人： SUN MICROSYSTEMS INC
发明人： GAUTHIER CLAUDE R , DESAI SHAISHAV A , HEALD RAYMOND
IPC分类号： G11C7/06 , H03F1/30
CPC分类号： G11C7/04 , G11C7/06 , G11C2207/065 , G11C2207/2254 , H03F1/30
摘要： A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.
摘要翻译：一种调整读出放大器的系统和方法包括向读出放大器提供放大控制参数。监视读出放大器的温度，并根据读出放大器的温度调整读出放大器的放大控制参数。

98. 发明申请

WO2004042917A2 SENSE AMPLIFIER THERMAL CORRECTION SCHEME 审中-公开
标题翻译：感测放大器热校正方案
公开(公告)号：WO2004042917A2
公开(公告)日：2004-05-21
申请号：PCT/US2003/034302
申请日：2003-10-29
申请人： SUN MICROSYSTEMS, INC.
发明人： GAUTHIER, Claude, R. , DESAI, Shaishav, A. , HEALD, Raymond
IPC分类号： H03F1/30
CPC分类号： G11C7/04 , G11C7/06 , G11C2207/065 , G11C2207/2254 , H03F1/30
摘要： A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.
摘要翻译：调整读出放大器的系统和方法包括提供放大控制参数给读出放大器。监测读出放大器的温度，并根据读出放大器的温度调整读出放大器的放大控制参数。

99. 发明申请

WO2003047104A1 ACTIVE TERMINATION CIRCUIT AND METHOD FOR CONTROLLING THE IMPEDANCE OF EXTERNAL INTEGRATED CIRCUIT TERMINALS 审中-公开
标题翻译：主动终止电路和控制外部集成电路端子阻抗的方法
公开(公告)号：WO2003047104A1
公开(公告)日：2003-06-05
申请号：PCT/US2002/037454
申请日：2002-11-20
申请人： MICRON TECHNOLOGY, INC.
发明人： MARTIN, Chris, G.
IPC分类号： H03K17/16
CPC分类号： G11C7/1084 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/1078 , G11C11/4093 , G11C2207/105 , G11C2207/2254
摘要： An active termination circuit (90) is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit (110) that generates a first control signal to set the impedance of another PMOS transistor (134) to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor (144) to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.
摘要翻译：有源终端电路（90）用于设定多个输入端的输入阻抗。每个输入端通过至少一个PMOS晶体管耦合到电源电压，并通过至少一个NMOS晶体管接地。晶体管的阻抗由产生第一控制信号以将另一PMOS晶体管（134）的阻抗设置为等于第一预定电阻的控制电路（110）来控制，并产生第二控制信号以设置阻抗的另一NMOS晶体管（144）等于第二预定电阻。第一控制信号用于控制所有PMOS晶体管，第二控制信号用于控制所有NMOS晶体管。结果，耦合到每个输入端的PMOS和NMOS晶体管分别具有对应于第一和第二电阻的阻抗。

100. 发明申请

WO2003012795A2 FUSE PROGRAMMABLE I/O ORGANIZATION 审中-公开
标题翻译：保险丝可编程I / O组织
公开(公告)号：WO2003012795A2
公开(公告)日：2003-02-13
申请号：PCT/EP2002/008560
申请日：2002-07-31
申请人： INFINEON TECHNOLOGIES AG
发明人： FRANKOWSKY, Gerd , VASQUEZ, Barbara
IPC分类号： G11C29/00
CPC分类号： G11C7/1045 , G11C2207/105 , G11C2207/2254
摘要： Circuitry using fuse and anti-fuse latches (62) for selecting the number of input/output channels (98, 109) after encapsulation is disclosed. The various embodiments allow conventional bond pads (14, 16, 18) to be used for initial selection of the number of input/output channels prior to encapsulation. However, by providing different selection signals (52, 54), the number of input/output channels may be changed by the user at any time after encapsulation. Other embodiments employ "enable" latch circuits (133,135) allow the initial selection by the users at any time after encapsulation, and then at least one more subsequent selection.
摘要翻译：公开了使用熔断器和反熔丝锁存器（62）进行封装后选择输入/输出通道数（98,109）的电路。各种实施例允许传统的接合焊盘（14,16,18）用于在封装之前的输入/输出通道的数量的初始选择。然而，通过提供不同的选择信号（52,54），输入/输出通道的数量可以由用户在封装之后的任何时间改变。其他实施例使用“使能”锁存电路（133,135）允许用户在封装之后的任何时间进行初始选择，然后进行至少一个以后的选择。

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