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91. 发明申请

WO2013069859A1 소거 대상 블록의 매핑 테이블을 저장하는 플래시 메모리 제어장치 및 방법 审中-公开
标题翻译：用于控制用于存储待擦除的块的映射表的闪存的设备和方法
公开(公告)号：WO2013069859A1
公开(公告)日：2013-05-16
申请号：PCT/KR2012/004568
申请日：2012-06-08
申请人： 한양대학교 산학협력단 , 송용호 , 정상혁
发明人： 송용호 , 정상혁
IPC分类号： G06F12/06 , G06F13/14 , G11C16/06
CPC分类号： G11C16/14 , G06F12/0246 , G11C16/04 , Y02D10/13
摘要： 소거 대상 블록의 매핑 테이블을 저장하는 플래시 메모리 제어장치 및 방법이 개시된다. 호스트 인터페이스부는 호스트와 제어신호 및 데이터를 송수신하고, 메모리 인터페이스부는 호스트로부터 수신된 제어신호에 따라 데이터를 플래시 메모리에 저장하거나 플래시 메모리로부터 독출한다. 저장부에는 플래시 메모리에서 데이터가 저장되는 복수의 페이지 각각의 논리 주소에 대응하는 복수의 엔트리에 각 페이지의 물리 주소가 기록된 주소 변환 테이블이 저장되며, 플래시 메모리의 각 블록의 물리 주소에 대응하는 복수의 엔트리에 각 블록에 포함된 무효 페이지의 개수 및 동일한 개수의 무효 페이지를 포함하는 다른 블록의 물리 주소가 기록된 블록 매핑 테이블과, 플래시 메모리의 각 블록에 포함된 무효 페이지의 개수에 대응하는 복수의 엔트리에 각 블록의 물리 주소가 기록된 소거 대상 블록 테이블이 더 저장된다.
摘要翻译：公开了一种用于控制闪速存储器以存储要擦除的块的映射表的装置和方法。主机接口单元向主机发送和接收控制信号和数据，并且存储器接口单元将数据存储在闪存中或响应于从主机接收的控制信号从闪存读取数据。存储单元存储其中每个页面的物理地址被记录在分别对应于其中存储有数据的闪存的多页的逻辑地址的多个条目中的地址转换表，并且还存储块映射表其中包括在每个块中的无效页面的数量和具有相同数量的无效页面的其他块的物理地址被记录在与要被擦除的闪速存储器和块表的每个块的物理地址相对应的多个条目中每个块的物理地址被记录在与闪存的每个块中包括的无效页的数量相对应的多个条目中。

92. 发明申请

WO2011127195A1 SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY 审中-公开
标题翻译：存储器中程序噪声减少的SAW形状多脉冲编程
公开(公告)号：WO2011127195A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/031452
申请日：2011-04-06
申请人： SANDISK CORPORATION , DONG, Yingda , FONG, Yupin, K. , HEMINK, Gerrit, Jan
发明人： DONG, Yingda , FONG, Yupin, K. , HEMINK, Gerrit, Jan
IPC分类号： G11C11/56 , G11C16/10
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C2211/5621 , G11C2211/5622
摘要： In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.
摘要翻译：在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。在子脉冲组之后执行验证操作。每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。

93. 发明申请

WO2011087901A2 ACCESS LINE DEPENDENT BIASING SCHEMES 审中-公开
标题翻译：访问线相关偏移计划
公开(公告)号：WO2011087901A2
公开(公告)日：2011-07-21
申请号：PCT/US2011/000046
申请日：2011-01-11
申请人： MICRON TECHNOLOGY, INC. , NGUYEN, Dzung, H.
发明人： NGUYEN, Dzung, H.
CPC分类号： G11C16/04 , G11C8/08 , G11C8/14 , G11C16/0483 , G11C16/08
摘要： The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array.
摘要翻译：本公开包括用于接入线偏置的方法，设备和系统。一个实施例包括：使用存储器设备外部的控制器选择特定的访问线路依赖偏置方案和相应的偏置条件，以用于对存储器件的存储器单元阵列执行访问操作，以及使用所选择的特定接入线相关偏置方案和相应的偏置条件。在一个或多个实施例中，所选择的特定访问线路依赖偏置方案和对应的偏置条件由至少部分地在阵列的目标访问线上的存储器设备外部的控制器选择。

94. 发明申请

WO2009086417A1 FLASH MEMORY TIMING PRE-CHARACTERIZATION FOR USE IN ORMAL OPERATION 审中-公开
标题翻译：闪存存储器时序预处理用于正常操作
公开(公告)号：WO2009086417A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/088223
申请日：2008-12-23
申请人： RAMBUS INC. , HAUKNESS, Brent, S. , SHAEFFER, Ian
发明人： HAUKNESS, Brent, S. , SHAEFFER, Ian
IPC分类号： G11C29/50 , G11C16/32
CPC分类号： G11C16/32 , G06F12/0246 , G06F2212/7201 , G11C16/04 , G11C16/107 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2029/4402
摘要： This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly. A mechanism is also provided for recalibrating memory previously marked. By minimizing variability, flash memory can be applied to a broader range of designs and potentially to a broader set of main memory applications.
摘要翻译：本公开提供了一种准确地确定与诸如设备，块或页面之类的闪速存储器细分有关的预期交易时间的方法。通过执行测试事务来对每个这样的单元的每个位进行编程，可以预先确定每个单元的最大预期编程时间并用于调度目的。例如，在简单的实现中，可以识别相对精确的经验测量的时间限制并用于有效地管理和调度闪速存储器事务，而不等待最终解决写入非响应页面的尝试。本公开还提供经验测量的最大闪存交易时间的其他用途，包括经由多个存储器模式和优先存储器; 例如，如果需要高性能模式，则可以容忍闪速存储器交易时间的低变化，并且可以相对快速地标记不满足这些原理的单元。还提供了一种用于重新校准之前标记的存储器的机制。通过最小化可变性，闪存可以应用于更广泛的设计，并可能应用于更广泛的主存储器应用。

95. 发明申请

WO2008150939A1 METHOD AND DEVICE FOR PROTECTING INFORMATION CONTAINED IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于保护集成电路中包含的信息的方法和设备
公开(公告)号：WO2008150939A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/065183
申请日：2008-05-30
申请人： SUMMIT DESIGN SOLUTIONS, INC. , SMIGELSKI, Tom , COTNER, Dennis
发明人： SMIGELSKI, Tom , COTNER, Dennis
IPC分类号： G11C7/00
CPC分类号： G11C29/12 , G06F21/79 , G11C7/24 , G11C16/04 , G11C2029/3202
摘要： An integrated circuit and a method of protection of an integrated circuit provides for a test controller state machine (TCSM) to be coupled to a control structure and /or an input and /or an output of at least one data storage device of the integrated circuit. The TCSM monitors the state of the data storage device and, upon a test request to the integrated circuit, causes the information in the data storage device to be changed or blocked until the data storage device is deemed safe for access. Such an integrated circuit and method protects information contained in data storage devices of the integrated circuit from being revealed during testing of circuitry of the integrated circuit.
摘要翻译：集成电路和集成电路的保护方法为测试控制器状态机（TCSM）提供耦合到集成电路的至少一个数据存储设备的控制结构和/或输入和/或输出。 TCSM监视数据存储设备的状态，并且在对集成电路的测试请求时，导致数据存储设备中的信息被改变或阻止，直到数据存储设备被认为是安全的访问。这种集成电路和方法保护集成电路的数据存储设备中包含的信息在集成电路的电路测试期间不被泄漏。

96. 发明申请

WO2008027681A3 NON-VOLATILE MEMORY DEVICE AND METHOD HAVING BIT-STATE ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING 审中-公开
标题翻译：非易失性存储器装置和具有选择的最小化信号耦合的位状态分配的方法
公开(公告)号：WO2008027681A3
公开(公告)日：2008-12-04
申请号：PCT/US2007074867
申请日：2007-07-31
申请人： MICRON TECHNOLOGY INC , NAZARIAN HAGOP A
发明人： NAZARIAN HAGOP A
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C2211/5641 , G11C2211/5643 , G11C2211/5647
摘要： A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row.
摘要翻译：非易失性存储器件以使寄生信号的耦合最小化的方式对每行中的存储器单元进行编程。控制逻辑单元使用通过评估将被写入行中的单元的数据而选择的一组位状态分配来对单元中的单元进行编程。控制逻辑单元通过确定将被编程到与写入数据相对应的多个位状态中的每一个的行中的单元的数量来执行该评估。然后控制逻辑单元选择一组位状态分配，这将导致分配给每个位状态的编程电平与该行状态下用该位状态编程的存储单元的数量成反比。然后使用所选的一组位状态来编程该行中的存储单元。

97. 发明申请

WO2008083131A3 METHOD FOR PROGRAMMING WITH INITIAL PROGRAMMING VOLTAGE BASED ON TRIAL 审中-公开
标题翻译：基于试验的初始编程电压编程方法
公开(公告)号：WO2008083131A3
公开(公告)日：2008-08-28
申请号：PCT/US2007088777
申请日：2007-12-24
申请人： SANDISK CORP , KAMEI TERUHIKO , LI YAN
发明人： KAMEI TERUHIKO , LI YAN
IPC分类号： G11C29/50 , G11C11/56 , G11C16/10 , G11C16/12
CPC分类号： G11C29/50 , G11C11/5628 , G11C16/04 , G11C16/10 , G11C29/028 , G11C29/50004 , G11C2029/0409
摘要： A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a second set of non-volatile storage elements (which may or may not include the first set).
摘要翻译：对第一组一个或多个非易失性存储元件执行试用编程过程以测试非易失性存储系统的使用。基于该试验编程，编程信号通过调整其初始量值来校准。然后使用校准的编程信号来编程第二组非易失性存储元件（其可以包括或不包括第一组）。

98. 发明申请

WO2008100602A1 EMBEDDED ARCHITECTURE WITH SERIAL INTERFACE FOR TESTING FLASH MEMORIES 审中-公开
标题翻译：带有串行接口的嵌入式结构，用于测试闪存
公开(公告)号：WO2008100602A1
公开(公告)日：2008-08-21
申请号：PCT/US2008/002057
申请日：2008-02-15
申请人： ATMEL CORPORATION , REGGIORI, Riccardo , TASSAN CASER, Fabio , MARSELLA, Mirella , MARZIANI, Monica
发明人： REGGIORI, Riccardo , TASSAN CASER, Fabio , MARSELLA, Mirella , MARZIANI, Monica
IPC分类号： G11C29/12 , G11C29/32 , G11C29/00
CPC分类号： G11C29/32 , G11C16/04 , G11C29/1201 , G11C29/16 , G11C29/4401 , G11C29/789 , G11C2029/3602
摘要： A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers.
摘要翻译：闪速存储器件包括闪存阵列，一组非易失性冗余寄存器，串行接口和耦合到串行接口的测试逻辑，该测试逻辑被配置为从外部测试器接收一组串行命令; 擦除数组; 使用测试模式对阵列进行编程; 读取阵列并将结果与预期结果进行比较以识别错误; 通过替换阵列的冗余行或列来确定是否可以修复错误，如果是，则生成冗余信息; 并将冗余信息编程到非易失性冗余寄存器中。

99. 发明申请

WO2008033693A3 NON-VOLATILE MEMORY AND METHOD FOR LINEAR ESTIMATION OF INITIAL PROGRAMMING VOLTAGE 审中-公开
标题翻译：非易失性存储器和初始编程电压线性估计方法
公开(公告)号：WO2008033693A3
公开(公告)日：2008-08-07
申请号：PCT/US2007077449
申请日：2007-08-31
申请人： SANDISK CORP , TU LOC , HOOK CHARLES MOANA , LI YAN
发明人： TU LOC , HOOK CHARLES MOANA , LI YAN
IPC分类号： G11C16/12 , G11C16/04 , G11C16/34 , G11C29/02 , G11C29/50
CPC分类号： G11C11/5628 , G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C29/02 , G11C29/021 , G11C29/028
摘要： In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.
摘要翻译：在非易失性存储器中，通过阶梯波形的一系列电压脉冲来连续地编程字线上的选定页面，同时在脉冲之间进行验证，直到页面被验证为指定图案。页面编程验证时的编程电压将是估计页面启动编程电压的初始值。通过在第二遍中使用来自第一遍的估计进一步改进估计。此外，当测试超过多个块时，基于块的类似几何位置的字线采样可以产生针对更快编程页面优化的起始编程电压。

100. 发明申请

WO2008089157A2 COLUMN LEAKAGE COMPENSATION IN A SENSING CIRCUIT 审中-公开
标题翻译：感应电路中的柱泄漏补偿
公开(公告)号：WO2008089157A2
公开(公告)日：2008-07-24
申请号：PCT/US2008051023
申请日：2008-01-14
申请人： ATMEL CORP , BEDARIDA LORENZO , MOSTOLA MARIA , MANFRE DAVIDE , FERRARIO DONATO
发明人： BEDARIDA LORENZO , MOSTOLA MARIA , MANFRE DAVIDE , FERRARIO DONATO
IPC分类号： G11C16/28 , G11C7/06 , G11C29/00
CPC分类号： G11C29/12 , G11C7/062 , G11C7/12 , G11C16/04 , G11C16/26
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.
摘要翻译：感测电路。在一个实施例中，感测电路包括存储电路，其包括吸收第一泄漏电流的第一位线，耦合到存储器电路的补偿装置和耦合到补偿装置的补偿电路。补偿电路包括吸收与第一泄漏电流匹配的第二漏电流的第二位线。补偿装置用于基于第二泄漏电流补偿通过电流的第一泄漏电流。根据本文公开的系统和方法，在确定存储单元的状态时，补偿装置和补偿电路可以防止错误。

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