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1. 发明申请

US20020184558A1 SUBSTRATE NOISE ISOLATION USING SELECTIVE BURIED DIFFUSIONS 审中-公开
标题翻译：使用选择性BURIED DIFFUSIONS的基础噪声分离
公开(公告)号：US20020184558A1
公开(公告)日：2002-12-05
申请号：US09871407
申请日：2001-05-31
申请人： Philips Semiconductor, Inc.
发明人： D.C. Sessions
IPC分类号： H04L001/22
CPC分类号： H01L21/823878 , H01L21/761
摘要： A mixed-signal CMOS integrated semiconductor device exhibits reduced substrate noise coupling between digital and analog circuit functions using selectively formed isolated, high-impurity buried regions between substrate and epitaxial layers. The impedance within the high-impurity regions is relatively lower than the impedance between high-impurity regions, thereby reducing noise-induced potentials, and latchup, within high-impurity regions and noise-induced currents between high-impurity regions. An attenuation network is effectively formed in the semiconductor device layers to reduce noise coupling, the impedance within the high-impurity region acting as the pi attenuation network shunt path. High-impurity regions are formed by selectively diffusing or implanting impurities into bulk lightly-doped, silicon substrate layer prior to growing an epitaxial layer. The high-impurity regions, substrate and epitaxial layers are all of the same conductivity type.
摘要翻译：混合信号CMOS集成半导体器件使用在衬底和外延层之间的选择性形成的隔离，高杂质掩埋区域，减少了数字和模拟电路功能之间的衬底噪声耦合。高杂质区域内的阻抗相对低于高杂质区域之间的阻抗，从而降低高杂质区域内高噪声感应电位和闭锁以及高杂质区域之间的噪声感应电流。在半导体器件层中有效地形成衰减网络以减少噪声耦合，高杂质区域内的阻抗作为π衰减网络分流路径。在生长外延层之前，通过选择性地将杂质掺杂到体积轻掺杂的硅衬底层中来形成高杂质区。高杂质区，衬底和外延层都是相同的导电类型。

2. 发明申请

US20020184411A1 Automatic upgradeable UART circuit arrangement 有权
标题翻译：可自动升级的UART电路布置
公开(公告)号：US20020184411A1
公开(公告)日：2002-12-05
申请号：US09870917
申请日：2001-05-31
申请人： Philips Semiconductor, Inc.
发明人： Neal T. Wingen , Eric Lai , Arnaud Moser , Ronald De Vries , Ramaswamy Subramanian
IPC分类号： G06F003/00
CPC分类号： G06F13/385
摘要： A configurable universal asynchronous receiver/transmitter (UART) facilitates efforts to upgrade UART functionality in the field and replace older UART devices. In one example embodiment, an integrated circuit includes a universal asynchronous receiver/transmitter configured and arranged to operate in one of a plurality of modes, with each mode being selectable in response to mode-selecting data. The integrated circuit device includes an interface circuit electrically connected to the universal asynchronous receiver/transmitter and adapted to present the mode-selecting data to the universal asynchronous receiver/transmitter. The integrated circuit device also includes a selection circuit adapted to enable the mode-selecting data to pass from the interface circuit to the universal asynchronous receiver/transmitter.
摘要翻译：可配置的通用异步收发器（UART）有助于在现场升级UART功能，并替代旧的UART设备。在一个示例实施例中，集成电路包括配置和布置为以多种模式之一操作的通用异步接收器/发射器，每种模式可响应于模式选择数据而选择。集成电路装置包括电连接到通用异步接收器/发射器并且适于将模式选择数据呈现给通用异步接收器/发射器的接口电路。集成电路装置还包括适于使模式选择数据从接口电路传递到通用异步接收器/发送器的选择电路。

3. 发明申请

US20020136290A1 Pulse-width modulation with feedback to toggle module 审中-公开
标题翻译：脉冲宽度调制与反馈到切换模块
公开(公告)号：US20020136290A1
公开(公告)日：2002-09-26
申请号：US09815145
申请日：2001-03-22
申请人： Philips Semiconductor, Inc.
发明人： William G. Houghton
IPC分类号： H03K007/08
CPC分类号： H03K7/08 , G06F1/025
摘要： A pulse-width modulation technique uses a counter load value that alternates between a duty-cycle defining value and its complement. In one embodiment, a pulse-width modulated signal is produced as a function of a control signal used to reload the counter in response to the counter reaching an overflow threshold value. This approach includes storing the counter load value and counting relative to a logic circuit output value which corresponds to either the load value or its complement. The counting is reinitiated using the logic circuit output in response to the counter reaching an overflow threshold value. A specific example application of the above type of PWM approach is directed to implementation in otherwise conventional up/down digital counters such as exists in 80C51-type microcontrollers.
摘要翻译：脉冲宽度调制技术使用在占空比定义值与其补码之间交替的反向负载值。在一个实施例中，响应于计数器达到溢出阈值，产生用于重新加载计数器的控制信号的函数的脉冲宽度调制信号。该方法包括存储计数器负载值和相对于对应于负载值或其补码的逻辑电路输出值的计数。响应于计数器达到溢出阈值，使用逻辑电路输出重新开始计数。上述类型的PWM方法的具体示例应用涉及在诸如存在于80C51型微控制器中的常规上/下数字计数器中的实现。

4. 发明申请

US20020184275A1 Reconfigurable digital filter having multiple filtering modes 失效
标题翻译：具有多种过滤模式的可重构数字滤波器
公开(公告)号：US20020184275A1
公开(公告)日：2002-12-05
申请号：US09871198
申请日：2001-05-31
申请人： Philips Semiconductor, Inc.
发明人： Santanu Dutta , David Molter
IPC分类号： G06F017/10
CPC分类号： H03H17/0275 , H03H17/0294
摘要： A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear. In a more specific embodiment the filtering modes include polyphase filtering and general purpose filtering applications (such as FIR filtering), and in another more specific embodiment the filtering modes include polyphase direct filtering, polyphase transposed filtering, and at least one general purpose filtering. A specific example application of the above type of digital filter is directed to filtering video pixel components, for example, in resizing a horizontal line of pixels.
摘要翻译：硬件可配置的数字滤波器适用于提供多种过滤模式。在一个实施例中，数字滤波器包括基于寄存器的逻辑电路阵列，计算电路和模式选择电路。通过重新配置逻辑电路和计算电路内的数据流，模式选择电路在多个滤波模式的不同之间切换数字滤波器。乘法和加法逻辑电路中的每一个具有输出和输入，其可选择性地耦合到沿着Y方向的乘法和加法逻辑电路中的另一个，其选择性响应于模式选择电路，用于将寄存器布置为功能线性或功能非线性。在更具体的实施例中，滤波模式包括多相滤波和通用滤波应用（例如FIR滤波），并且在另一个更具体的实施例中，滤波模式包括多相直接滤波，多相转置滤波和至少一个通用滤波。上述类型的数字滤波器的具体示例应用涉及滤波视频像素分量，例如，在调整水平线像素的大小中。

5. 发明申请

US20020184543A1 Power and frequency adjustable UART device 有权
标题翻译：电源和频率可调UART设备
公开(公告)号：US20020184543A1
公开(公告)日：2002-12-05
申请号：US09870918
申请日：2001-05-31
申请人： Philips Semiconductor, Inc.
发明人： Neal T. Wingen
IPC分类号： G06F001/26 , G06F001/32
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： The present invention embodiment comprises an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant. In one example embodiment, an arrangement of a plurality of integrated circuit devices includes a first integrated circuit device driven by a first clock signal at a first clock rate. The arrangement contains a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal. The arrangement also includes a universal asynchronous receiver/transmitter (UART) chip with a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal. The UART chip also encompasses a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit. The UART chip also houses a data-storage-register circuit adapted to output status data to the parallel data bus, the status data being indicative of states of at least one of the serial communication circuit and the parallel bus interface circuit. The arrangement of integrated circuit devices further includes a clock control circuit adapted to reduce the first clock rate in response to a clock control signal. By reducing the first clock rate, the UART chip is configured to operate in a power-reduced mode while the serial communication circuit concurrently communicates serial data at the second rate.
摘要翻译：本发明实施例包括具有UART装置的集成电路的布置，其可配置为在串行数据通信的时钟频率保持恒定的同时以功率降低模式工作。在一个示例实施例中，多个集成电路器件的布置包括以第一时钟速率由第一时钟信号驱动的第一集成电路器件。该装置包含耦合以响应于第一时钟信号与第一集成电路装置通信的并行数据总线。该装置还包括具有串行通信电路的通用异步收发器（UART）芯片，该串行通信电路适于以由第二时钟信号定义的第二速率传送串行数据。 UART芯片还包括响应于第一时钟信号并且适于在并行数据总线和串行通信电路之间传递数据的并行总线接口电路。 UART芯片还容纳适于将状态数据输出到并行数据总线的数据存储寄存器电路，状态数据指示串行通信电路和并行总线接口电路中的至少一个的状态。集成电路装置的布置还包括时钟控制电路，其适于响应于时钟控制信号而减小第一时钟速率。通过降低第一时钟速率，UART芯片被配置为在功率降低模式下工作，而串行通信电路以第二速率同时传送串行数据。

6. 发明申请

US20020181641A1 Integrated circuit arrangement with feature control 有权
标题翻译：具有特征控制的集成电路布置
公开(公告)号：US20020181641A1
公开(公告)日：2002-12-05
申请号：US09871231
申请日：2001-05-31
申请人： Philips Semiconductor, Inc.
发明人： Neal T. Wingen
IPC分类号： H04L023/00
CPC分类号： G06F13/385
摘要： An integrated circuit arrangement is reconfigurable in the field to operate in one of a plurality of modes, including a test mode, in response to mode-selecting codes presented via a temporary register in the circuit. In one example embodiment, an arrangement of integrated circuits includes a reconfigurable integrated circuit configured and arranged to operate in one of a plurality of modes. The reconfigurable integrated circuit includes a register adapted to store data for temporary use, with each operating mode of the reconfigurable circuit being selectable in response to mode-selecting data code. An interface circuit is electrically connected to the reconfigurable integrated circuit and is adapted to present the mode-selecting data code to the reconfigurable integrated circuit. A selection circuit is adapted to enable the interface circuit to pass mode-selecting data to the reconfigurable integrated circuit. The selection circuit is also adapted to detect when a series of data writes to the register corresponds to the mode-selecting data code and, in response, to reconfigure the integrated circuit to operate in one of the plurality of modes.
摘要翻译：集成电路装置在现场可重新配置，以响应于通过电路中的临时寄存器呈现的模式选择代码，以多种模式之一操作，包括测试模式。在一个示例实施例中，集成电路的布置包括被配置和布置成以多种模式之一操作的可重构集成电路。可重构集成电路包括适于存储用于临时使用的数据的寄存器，可重新配置电路的每个操作模式可响应于模式选择数据代码来选择。接口电路电连接到可重构集成电路，并且适于将模式选择数据代码呈现给可重构集成电路。选择电路适于使接口电路能够将模式选择数据传送到可重构集成电路。选择电路还适于检测何时一系列对寄存器的数据写入对应于模式选择数据代码，并且作为响应，重新配置集成电路以以多种模式之一进行操作。

7. 发明申请

US20020145454A1 Reset circuit and method therefor 有权
标题翻译：复位电路及其方法
公开(公告)号：US20020145454A1
公开(公告)日：2002-10-10
申请号：US09826570
申请日：2001-04-05
申请人： Philips Semiconductor, Inc.
发明人： Rune H. Jensen
IPC分类号： H03L007/00
CPC分类号： G06F1/24
摘要： The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset signal generator is coupled to a clock module having an external clock reference and to each of the peripheral devices. A reset clock signal having the reference clock frequency is sent to each of the peripheral devices via clock outputs at the clock module. A synchronization module at each of the peripheral devices is adapted to synchronize the reset signal among all peripheral devices using the clock signal. The clock module holds the reset clock signal for a selected amount of time, and then releases the signal from the external clock. The reset signals are then simultaneously released at each of the peripheral devices, making possible a smooth transition from reset.
摘要翻译：使用模块化，可扩展，直接实现并允许简单和安全的物理设计实现的电路布置来改善电子电路的可操作性和可扩展性。根据本发明的一个示例性实施例，复位方法和系统用于在可能采用类似的和/或不同的复位策略的几个外围设备上实现复位。复位信号发生器耦合到具有外部时钟参考的时钟模块和每个外围设备。具有参考时钟频率的复位时钟信号通过时钟模块的时钟输出发送到每个外围设备。每个外围设备的同步模块适于使用时钟信号来使所有外围设备之间的复位信号同步。时钟模块将复位时钟信号保持一段选定的时间，然后从外部时钟释放信号。然后，在每个外围设备上同时释放复位信号，从而能够从复位平稳过渡。

8. 发明申请

US20020144072A1 Dynamically configurable page table 有权
标题翻译：动态配置页表
公开(公告)号：US20020144072A1
公开(公告)日：2002-10-03
申请号：US09822889
申请日：2001-03-30
申请人： Philips Semiconductor, Inc.
发明人： Vishal Anand
IPC分类号： G06F012/10
CPC分类号： G06F12/0215
摘要： The reliability and operability of semiconductor devices is improved using a circuit arrangement and method that improves the ability to manage data storage and retrieval. According to one example embodiment of the present invention, a memory device includes a dynamically configurable page table having a plurality of pages. The page table is dynamically configurable to at least two organizations, and each page includes a multitude of memory storage locations adapted to store data. A controller is adapted to track memory requests and to configure the page table to one of the at least two organizations during a memory refresh cycle, wherein the configuration is effected in response to the tracked memory requests. In this manner, the page table can be adapted to improve the effectiveness and speed of data storage and retrieval.
摘要翻译：使用提高管理数据存储和检索能力的电路装置和方法，提高了半导体器件的可靠性和可操作性。根据本发明的一个示例性实施例，存储器设备包括具有多个页面的动态配置页面表。该页表可以动态地配置到至少两个组织，并且每个页面包括适于存储数据的大量存储器存储位置。控制器适于跟踪存储器请求并且在存储器刷新周期期间将页表配置为至少两个组织中的一个，其中响应于所跟踪的存储器请求来实现配置。以这种方式，页表可以适应于提高数据存储和检索的有效性和速度。

9. 发明申请

US20020184549A1 Parallel data communication having multiple sync codes 有权
标题翻译：具有多个同步码的并行数据通信
公开(公告)号：US20020184549A1
公开(公告)日：2002-12-05
申请号：US09871117
申请日：2001-05-31
申请人： Philips Semiconductor, Inc.
发明人： Gregory E. Ehmann
IPC分类号： G06F001/12 , H04L005/00 , G06F013/42
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/04 , H04L25/4908
摘要： A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.
摘要翻译：高速并行数据通信方法通过自动对准传输数字数据来克服偏斜问题。在一个示例实施例中，并行总线具有适于从数据文件传送数字数据的并行总线以及同步时钟信号。为了校准同步，发送模块通过接收模块传输根据时钟信号的边沿进行采样和验证的同步码，然后用于相对于同步码对时钟信号的边沿进行时间调整。执行同步代码以在传送了每个同步码的情况下切换总线。

10. 发明申请

US20020184413A1 Circuit arrangement and method for improving data management in a data communications circuit 失效
标题翻译：用于改善数据通信电路中的数据管理的电路布置和方法
公开(公告)号：US20020184413A1
公开(公告)日：2002-12-05
申请号：US09871027
申请日：2001-05-31
申请人： Philips Semiconductor, Inc.
发明人： Neal T. Wingen
IPC分类号： G06F003/00
CPC分类号： G06F13/385
摘要： A circuit arrangement improves CPU efficiency by processing data through a FIFO circuit of a UART chip using a CPU adapted to detect, and respond with various options to, the current storage capacity of the FIFO circuit. In one example embodiment, a circuit arrangement includes a universal asynchronous receiver/transmitter (UART) chip having a FIFO circuit and an arithmetic logic unit (ALU) adapted to generate an N-bit variable binary signal, wherein the binary signal varies as a function of a current storage capacity of the FIFO circuit. The circuit arrangement further includes a control circuit communicatively coupled with the UART chip that is adapted to read the N-bit variable binary signal and, in response, to control the data flow through the FIFO circuit.
摘要翻译：电路装置通过使用CPU的UART电路的FIFO电路处理数据来提高CPU效率，该CPU适用于检测FIFO电路的当前存储容量并对其进行各种选择。在一个示例实施例中，电路装置包括具有FIFO电路和适于产生N位可变二进制信号的算术逻辑单元（ALU）的通用异步接收器/发射器（UART）芯片，其中二进制信号作为一个功能变化的当前存储容量的FIFO电路。电路装置还包括与UART芯片通信耦合的控制电路，该控制电路适于读取N位可变二进制信号，并且响应于控制通过FIFO电路的数据流。

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