专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20040196682A1 Semiconductor unit having two device terminals for every one input/output signal 失效
标题翻译：半导体单元具有用于每一个输入/输出信号的两个器件端子
公开(公告)号：US20040196682A1
公开(公告)日：2004-10-07
申请号：US10672551
申请日：2003-09-26
申请人： Elpida Memory, Inc. , Hitachi, Ltd. , Renesas Eastern Japan Semiconductor, Inc.
发明人： Seiji Funaba , Hisashi Abo , Takao Ono , Koji Hosokawa , Yoji Nishio , Atsushi Nakamura , Tomohiko Sato
IPC分类号： G11C011/24
CPC分类号： H01L25/105 , H01L23/50 , H01L23/552 , H01L23/60 , H01L23/64 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2224/49171 , H01L2224/85399 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/13091 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/19032 , H01L2924/19041 , H01L2924/19051 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K1/112 , H05K1/14 , H05K1/181 , H05K2201/09236 , H05K2201/10159 , H05K2201/10545 , Y02P70/611 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.
摘要翻译：构成存储器件的半导体单元具有存储芯片，具有三个布线层的封装基板。电源表面（VDD表面）和（GND表面）被布线在封装衬底上，而封装内的DQ总线布线在两个电源表面之间的中间层上。存储器件每一个封装内DQ总线具有两个DQ引脚。封装内的DQ总线通过通孔连接到存储器芯片的信号端子焊盘。鉴于两个DW引脚，用于将封装内DQ DQ总线与信号端子焊盘连接的通孔构成分支线。

2. 发明申请

US20030031060A1 Register without restriction of number of mounted memory devices and memory module having the same 有权
标题翻译：在不限制安装的存储器件的数量和具有相同的存储器模块的情况下进行注册
公开(公告)号：US20030031060A1
公开(公告)日：2003-02-13
申请号：US10206823
申请日：2002-07-29
申请人： ELPIDA MEMORY, INC., HITACHI TOHBU SEMICONDUCTOR
发明人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
IPC分类号： G11C007/00
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C2207/107
摘要： First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of 1/2 of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of singals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.
摘要翻译：第一和第二预处理触发器通过具有外部时钟信号的1/2的频率及其反时钟的时钟来锁存输入到寄存器的命令/地址信号。因此，命令/地址信号被分解为一组暂时具有两次的信号。例如，该组信号之一仅具有奇数命令/地址信号的数据内容，而另一个仅具有偶数个命令/地址信号的数据内容。由于该组信号具有两个命令/地址信号的周期，所以第一和第二后处理触发器可以根据由延迟锁定环电路产生的内部时钟信号来锁存信号，时间和保持时间充分确保。

3. 发明申请

US20030221044A1 Memory system, module and register 有权
标题翻译：内存系统，模块和寄存器
公开(公告)号：US20030221044A1
公开(公告)日：2003-11-27
申请号：US10427090
申请日：2003-04-30
申请人： Elpida Memory, Inc.
发明人： Yoji Nishio , Kayoko Shibata , Seiji Funaba
IPC分类号： H04L005/00
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1093
摘要： Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAMnull1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register. Alternatively, control is made for switching between the replica (replica 1) provided in the register and an output unit associated with the replica, depending on the frequency being used, so as to cope with both frequencies simply by providing one sort of the module and one sort of the register.
摘要翻译：公开了一种存储器命令地址系统和存储器模块，其不仅可以用于266MHzCLK，而且可以用于200MHzCLK，其中PLL，寄存器和DRAM的输入部分中的时钟定时彼此匹配，在寄存器中提供DLL（延迟锁定环），控制来自寄存器的CA信号的输出定时，使得CA信号的建立时间余量和保持时间裕度相对于时钟信号具有额外的等待时间 DRAM = 1.5或2.0彼此相等，使得例如266MHz的时钟操作成为可能。如果使用266MHz和200MHz，通过考虑时序预算，进行控制以延迟输入到触发器的CA信号的定时，该触发器接收提供给触发器的内部时钟信号（intCLK）用于确定来自寄存器的CA信号输出定时。或者，根据所使用的频率，进行控制，用于在寄存器中提供的副本（副本1）和与副本相关联的输出单元之间进行切换，从而简单地通过提供一种模块和一种登记册。

4. 发明申请

US20030052345A1 Semiconductor apparatus capable of preventing occurrence of multiple reflection, driving method, and setting method thereof 有权
标题翻译：能够防止发生多重反射的半导体装置，驱动方法及其设定方法
公开(公告)号：US20030052345A1
公开(公告)日：2003-03-20
申请号：US10226777
申请日：2002-08-23
申请人： Elpida Memory, Inc.
发明人： Satoshi Isa , Seiji Funaba
IPC分类号： H01L029/80
CPC分类号： H04L25/0278 , H04L25/028
摘要： A semiconductor apparatus comprises a resistor formed in a driver to connect a driving device to a transmission line connecting the driver to a receiver. The resistor has resistance considerably larger than on-state resistance of the driving device on condition that the resistor matches output impedance of the driver with impedance of the transmission line. The transmission line has length decided so that a reflected wave from a receiver-side end of the transmission line reaches the driver while a driving signal supplied to the driver has a logical high or low level.
摘要翻译：半导体装置包括形成在驱动器中的电阻器，用于将驱动装置连接到将驱动器连接到接收器的传输线。在电阻与传动线阻抗匹配的驱动器的输出阻抗匹配的情况下，电阻器的阻值远大于驱动装置的通态电阻。传输线的长度被确定，使得来自传输线的接收机侧端的反射波到达驱动器，同时提供给驱动器的驱动信号具有逻辑高或低电平。

5. 发明申请

US20030043683A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20030043683A1
公开(公告)日：2003-03-06
申请号：US10234261
申请日：2002-09-04
申请人： ELPIDA MEMORY, INC.
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G11C005/06 , G11C008/00
CPC分类号： G11C7/1048 , G11C5/063 , G11C7/10 , G11C11/4093
摘要： In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.
摘要翻译：在具有控制器和多个存储器模块的存储器件中，两者都被安装在母板上，通过抑制由信号反射引起的波形失真来执行高速操作。由于当控制器执行相对于存储器模块上的存储器单元的数据的写入/读取时发生信号反射，因此主动终端单元包括在控制器和存储器单元中。这些有源终端单元被提供用于数据总线和/或时钟总线，以便在存储器单元中终止这些总线。当要接收数据时，为控制器和存储单元提供的有效终端单元可能会处于非活动状态。

6. 发明申请

US20040264267A1 Signal transmitting system 失效
标题翻译：信号传输系统
公开(公告)号：US20040264267A1
公开(公告)日：2004-12-30
申请号：US10816187
申请日：2004-04-02
申请人： Elpida Memory, Inc.
发明人： Yoji Nishio , Seiji Funaba
IPC分类号： G11C029/00
CPC分类号： H04L5/16 , G11C7/1006 , H04L25/0278
摘要： Semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected by a bidirectional bus which is a transmission line. A driver is of a push-pull type and a reception side is CTT-terminated. If a terminating resistor is in conformity with the characteristic impedance of the transmission line, the on resistance of the driver is equal to or lower than the characteristic impedance. If the on resistance of the driver is in conformity with the characteristic impedance of the transmission line, the value of the terminating resistor is equal to or lower than the characteristic impedance of the transmission line. If the reception side is VTT-terminated, the value of the VTT is {fraction (1/2)} of a lower one of power supply voltages that are supplied to the respective semiconductor integrated circuit devices. The value of the terminating resistor is in conformity with the characteristic impedance of the transmission line. The semiconductor integrated circuit devices use a common reference voltage for determining the signal voltage.
摘要翻译：在不同电源电压下工作的半导体集成电路器件通过作为传输线的双向总线直接互连。驱动器是推挽式的，接收端是CTT端接的。如果终端电阻符合传输线的特性阻抗，则驱动器的导通电阻等于或低于特性阻抗。如果驱动器的导通电阻与传输线的特性阻抗一致，则终端电阻的值等于或低于传输线的特性阻抗。如果接收侧是VTT终止的，则VTT的值是提供给各个半导体集成电路器件的较低的一个电源电压的{分数（1/2）}。终端电阻的值与传输线的特性阻抗一致。半导体集成电路器件使用公共参考电压来确定信号电压。

7. 发明申请

US20040019758A1 Memory module and memory system suitable for high speed operation 失效
标题翻译：内存模块和内存系统适合高速运行
公开(公告)号：US20040019758A1
公开(公告)日：2004-01-29
申请号：US10630457
申请日：2003-07-29
申请人： Elpida Memory, Inc.
发明人： Kayoko Shibata , Yoji Nishio , Seiji Funaba
IPC分类号： G06F013/00
CPC分类号： H05K1/0246 , H05K2201/10022 , H05K2201/10159
摘要： A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by:Rsnull(Nnull1)nullZeffdimm/N, andRtermnullZeffdimmwhere N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by:Zmbnull(2Nnull1)nullZeffdimm/N2.
摘要翻译：存储器模块包括在引脚和总线的一端之间的尖端电阻器。多个存储器芯片在其两端之间连接到总线。终端电阻连接到总线的另一端。触发电阻的阻抗Rs和终端电阻的终端电阻Rterm由下式给出：Rs =（N-1）xZeffdimm / N，Rterm = Zeffdimm其中N表示存储器系统中的存储器模块的数量; 和Zeffdimm，由总线和存储器芯片组成的存储芯片布置部分的有效阻抗。在存储器系统中，存储器模块以连接方式连接到主板上的存储器控制器。主板的接线阻抗Zmb由下式给出：Zmb =（2N-1）xZeffdimm / N <2。

8. 发明申请

US20030080774A1 Input/output circuit, reference-voltage generating circuit, and semiconductor integrated circuit 有权
标题翻译：输入/输出电路，参考电压发生电路和半导体集成电路
公开(公告)号：US20030080774A1
公开(公告)日：2003-05-01
申请号：US10279817
申请日：2002-10-25
申请人： ELPIDA MEMORY, INC.
发明人： Seiji Funaba
IPC分类号： H03K019/003
CPC分类号： H04L25/028 , H03K19/018592 , H04L25/0278 , H04L25/0292
摘要： Disclosed is an input/output circuit having a terminating circuit that contributes to a smaller chip area. The input/output includes an output buffer having a first series circuit, which comprises a first transistor and a resistor and a second series circuit, which comprises a second transistor and a resistor, connected in parallel between a high-potential power supply and an input/output pin, as well as a third series circuit, which comprises a third transistor and a resistor and a fourth series circuit, which comprises a fourth transistor and a resistor, connected in parallel between the input/output pin and a low-potential power supply. The input/output circuit further includes an input buffer having an input terminal connected to the input/output pin, and a control circuit which, at the time of a signal output, performs control for supplying a signal, which is obtained by inverting the logic of output data, to gates of the first to fourth transistors, and which, at the time of a signal input, performs control for supplying the gates of the first and third transistors with the high-potential power supply voltage and low-potential power supply voltage, respectively, and the gates of the second and fourth transistors with the low-potential power supply voltage and high-potential power supply voltage, respectively.
摘要翻译：公开了具有有助于较小芯片面积的终端电路的输入/输出电路。该输入/输出包括具有第一串联电路的输出缓冲器，该第一串联电路包括第一晶体管和电阻器以及第二串联电路，该第二串联电路包括并联连接在高电位电源和输入端之间的第二晶体管和电阻器 /输出引脚，以及第三串联电路，其包括第三晶体管和电阻器以及第四串联电路，其包括第四晶体管和电阻器，并联连接在输入/输出引脚和低电位电源供应。输入/输出电路还包括具有连接到输入/输出引脚的输入端的输入缓冲器，以及在信号输出时进行用于提供信号的控制的控制电路，该控制电路通过将逻辑的输出数据输出到第一至第四晶体管的栅极，并且在信号输入时，执行用于向第一和第三晶体管的栅极提供高电位电源电压和低电位电源的控制分别具有低电位电源电压和高电位电源电压的第二和第四晶体管的栅极。

9. 发明申请

US20030025540A1 Register capable of corresponding to wide frequency band and signal generating method using the same 有权
标题翻译：对应于宽频带的寄存器和使用其的信号生成方法
公开(公告)号：US20030025540A1
公开(公告)日：2003-02-06
申请号：US10206822
申请日：2002-07-29
申请人： ELPIDA MEMORY, INC.
发明人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
IPC分类号： H03L007/06
CPC分类号： G11C5/04 , G11C5/00 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/222 , H03L7/0814
摘要： A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.
摘要翻译：假定安装的存储器件的数量的最大值，并且外部延迟副本的值被固定和设置。将期望的频带划分为多个子频带，并且每个子频带切换并使用输出缓冲器和内部延迟副本的延迟时间，从而将实际最大值和实际最小值设置为内部延迟复制。选择引脚可以选择内部延迟副本中的延迟时间。因此，可以充分确保在期望频带内的寄存器中的锁存操作中的延迟锁定环电路产生的内部时钟信号的建立时间和保持时间以及可允许数量的存储器件，而不考虑频率水平和安装的存储器件的数量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式