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1. 发明授权

US4125993A Digital display devices with remote updating 失效
标题翻译：具有远程更新功能的数字显示设备
公开(公告)号：US4125993A
公开(公告)日：1978-11-21
申请号：US702034
申请日：1976-07-02
申请人： Philip Emile, Jr.
发明人： Philip Emile, Jr.
IPC分类号： G04G3/02 , G04G9/08 , G04G99/00 , G04C3/00 , G04C13/04 , H04M15/38
CPC分类号： G04G99/006 , G04G3/025 , G04G9/082
摘要： Digital display devices and digital timepieces in which the display is remotely updated. The method permits continuous updating with simple and inexpensive TTL Logic and less frequent updating with microprocessor means. The remote updating signal can be transmitted through telephone means, broadcast means or other standard communications means to simultaneously update multiple digital displays.A single improved digital display device can be utilized as a master for controlling the display of multiple devices.
摘要翻译：显示器远程更新的数字显示设备和数字时计。该方法允许使用简单且便宜的TTL逻辑进行连续更新，并且使用微处理器手段更少地更新频率。远程更新信号可以通过电话装置，广播装置或其他标准通信装置传输，以同时更新多个数字显示器。

2. 发明授权

US4093992A Electronic wristwatch 失效
标题翻译：电子手表
公开(公告)号：US4093992A
公开(公告)日：1978-06-06
申请号：US739771
申请日：1976-11-08
申请人： Yoshikazu Kawamura , Akio Shimoi , Yuichiro Iwai
发明人： Yoshikazu Kawamura , Akio Shimoi , Yuichiro Iwai
IPC分类号： G04G5/04 , G04G3/02 , G04G5/00 , G04G9/00 , G04G13/02 , G04G17/02 , G04G17/04 , G04G99/00 , G06F15/02 , G06F7/48 , G04B19/30
CPC分类号： G04G21/08 , G04G13/02 , G04G3/025 , G04G9/0047 , G04G9/0076 , G06F15/0208
摘要： An electronic wristwatch having calculator circuitry operated by the time standard signals utilized to operate the timekeeping circuitry is provided. The electronic wristwatch includes a timing pulse generating circuit for producing a plurality of signals. Timekeeping circuitry is coupled to the timing pulse time standard signals produced thereby, for producing a plurality of timekeeping signals representive of actual time in response to at least one of the time standard signals being applied thereto. A digital display is provided for displaying actual time in response to at least some of the plurality of timekeeping signals being applied thereto. Calculator circuitry is provided for producing calculation signals representative of numerical information or a calculating function in response to receiving at least two of the time standard signals produced by the timing pulse generator means, the digital display being adapted to display the numerical information and calculating function in response to the calculating signals produced by the calculating circuitry being applied thereto.
摘要翻译：提供了一种具有由用于操作计时电路的时间标准信号操作的计算器电路的电子手表。电子手表包括用于产生多个信号的定时脉冲发生电路。计时电路与由此产生的定时脉冲时间标准信号耦合，用于响应于施加到其上的时间标准信号中的至少一个产生代表实际时间的多个计时信号。提供了数字显示器，用于响应于施加到其上的多个计时信号中的至少一些来显示实际时间。计算器电路被提供用于响应于接收由定时脉冲发生器装置产生的至少两个时间标准信号而产生表示数字信息或计算功能的计算信号，数字显示器适于显示数字信息和计算功能响应于由其应用的计算电路产生的计算信号。

3. 发明授权

US3798428A Electronic time-keeping apparatus 失效
标题翻译：电子保时器
公开(公告)号：US3798428A
公开(公告)日：1974-03-19
申请号：US3798428D
申请日：1972-03-20
申请人： SEIKOSHA KK
发明人： IZAWA M
IPC分类号： G04G3/02 , G04G5/04 , G06F7/385
CPC分类号： G04G3/022 , G04G3/025 , G04G5/043
摘要： An electronic time-keeping apparatus generating counting pulses for a time count. The counting pulses are stored in registers connected to input gates of adders that develop, from the counting pulses stored by the registers, output signals through gates corresponding to a time count. The adders develop carry signals that are temporarily stored by a carry memory register and are applied back to the adders under control of a carry signal controller and through the latter for developing the time count output of the adders for higher order places in the time count. The time count is displayed on visual display means as a time indication corresponding to the time count. Provision is made for initial counting errors by use of an automatic initial error preventive circuit that detects errors in the counting signals stored which may result from noise or at the start of the count and signals are developed that are applied to the adders thus varying the signal content received by the adders so that the time count output thereof is free of these initial errors. Control circuitry in the form of reset circuitry is provided for resetting the time count by applying signals at will to the adders to reset the time count output and thereby the time indication of the visual display means. The control circuitry includes time advancing circuitry by which the time count output is advanced by applying signals to the adders at will so that the time count indication is advanced and an advanced time or corrected time may be displayed. The apparatus may be embodied in small clocks.
摘要翻译：电子计时装置产生计时脉冲。计数脉冲存储在连接到加法器的输入门的寄存器中，从寄存器存储的计数脉冲中，通过对应于时间计数的门输出信号。加法器产生由进位存储器寄存器临时存储的进位信号，并在进位信号控制器的控制下被应用回到加法器，并且通过后者在时间计数中开发加法器的时间计数输出用于较高阶位置。时间计数在视觉显示装置上显示为对应于时间计数的时间指示。通过使用自动初始误差预防电路来提供初始计数误差，该电路检测存储的计数信号中可能由噪声或计数开始引起的信号的错误，并且信号被显影，从而改变信号由加法器接收的内容，使得其时间计数输出没有这些初始错误。提供复位电路形式的控制电路用于通过随意施加信号给加法器复位时间计数，以复位时间计数输出，从而重置视觉显示装置的时间指示。控制电路包括时间提前电路，通过这样的时间计数输出，通过随意地向加法器施加信号来提前时间计数输出，以便时间计数指示提前并且可以显示高级时间或校正时间。该装置可以以小时钟体现。

4. 发明授权

US4314161A Integrated shift register 失效
标题翻译：集成移位寄存器
公开(公告)号：US4314161A
公开(公告)日：1982-02-02
申请号：US53405
申请日：1979-06-29
申请人： Jacob Luscher
发明人： Jacob Luscher
IPC分类号： G04G3/02 , G11C19/18 , H03K21/10 , H03K23/46 , H03K23/66 , G11C19/28
CPC分类号： G04G3/025 , G11C19/186 , H03K21/10 , H03K23/46 , H03K23/66
摘要： The shift register has a very low power consumption. Each cell of the shift register has two stages, each comprising an MOS structure (T.sub.1 -T'.sub.1) which has two principal electrodes (Z.sub.00, Z.sub.1) respectively forming the input (Z.sub.oo) and the output (Z.sub.1) of the stage, and two control electrodes (k.sub.1, k'.sub.1) one of which (k.sub.1) can be connected to a bias source (P) and the other of which (k'.sub.1) is connected to the output electrode (Z.sub.1), and a capacitor (C.sub.1), one plate (Z.sub.1) of which is connected to the said output electrode (Z.sub.1) and the other plate (C.sub.1) of which receives one of two periodic signals .phi..sub.1 (t) and .phi..sub.2 (t) in phase opposition. The register is especially useful in a frequency divider circuit.
摘要翻译：移位寄存器具有非常低的功耗。移位寄存器的每个单元具有两级，每级包括具有分别形成输入（Zoo）和级的输出（Z1）的两个主电极（Z00，Z1）的MOS结构（T1-T'1），以及其中一个（k1）可以连接到偏置源（P）和另一个（k'1）连接到输出电极（Z1）的两个控制电极（k1，k'1）和电容器 C1），其一个板（Z1）连接到所述输出电极（Z1），另一个板（C1）接收相位相反的两个周期信号phi 1（t）和phi 2（t）中的一个。该寄存器在分频器电路中特别有用。

5. 发明授权

US4295056A Integrated frequency divider 失效
标题翻译：集成分频器
公开(公告)号：US4295056A
公开(公告)日：1981-10-13
申请号：US054230
申请日：1979-07-02
申请人： Jacob Luscher
发明人： Jacob Luscher
IPC分类号： G04G3/02 , G11C19/18 , H03K3/356 , H03K23/46 , H03K21/00 , H03K5/13
CPC分类号： G04G3/025 , G11C19/184 , H03K23/46 , H03K3/356017 , H03K3/356069
摘要： The frequency divider allows division of the frequency of two signals in phase opposition .phi..sub.1 (t) and .phi..sub.2 (t). A shift register 10 comprises an assembly of transistors and capacitors which form a plurality of cells connected one after the other, each cell being comprised of two identical stages which are connected in series and are supplied respectively by the periodic signals. Means for detecting particular stages of the register comprise the MOS transistors T.sub.8, T.sub.9, and T.sub.10. Means for producing a signal with a frequency which is a sub-multiple of that of the said periodic signals comprise the transistors T.sub.11 and T.sub.12, the transistor T.sub.13, the capacitor C.sub.7 and the capacitor C.sub.9. The divider is especially suitable for use in quartz oscillator watches.
摘要翻译：分频器允许在相位相反phi 1（t）和phi 2（t）中分离两个信号的频率。移位寄存器10包括晶体管和电容器的组件，其形成多个彼此连接的单元，每个单元由串联连接并分别由周期信号提供的两个相同级构成。用于检测寄存器的特定级的装置包括MOS晶体管T8，T9和T10。用于产生具有所述周期信号的频率的子频率的信号的装置包括晶体管T11和T12，晶体管T13，电容器C7和电容器C9。分频器特别适用于石英振荡器手表。

6. 发明授权

US4092819A Electronic timepiece circuit 失效
标题翻译：电子钟表电路
公开(公告)号：US4092819A
公开(公告)日：1978-06-06
申请号：US702198
申请日：1976-07-02
申请人： Tsuneo Takase
发明人： Tsuneo Takase
IPC分类号： G04G3/02 , G04G99/00 , G04C3/00 , G04C21/00 , H03K21/32
CPC分类号： G04G3/025
摘要： An electronic timepiece circuit wherein time data is shifted through a closed loop formed of a memory circuit, correction circuit and adder to count time upon receipt of a timing pulse, the memory circuit being composed of a plurality of static complementary MOS transistor type random access memory cells arranged in matrix form.
摘要翻译：一种电子钟表电路，其中时间数据通过由存储器电路，校正电路和加法器构成的闭环移位，以在接收到定时脉冲时对时间进行计数，该存储电路由多个静态互补MOS晶体管型随机存取存储器细胞以矩阵形式排列。

7. 发明授权

US3986333A Electronic digital clock 失效
标题翻译：电子数字时钟
公开(公告)号：US3986333A
公开(公告)日：1976-10-19
申请号：US479498
申请日：1974-06-14
申请人： Seiji Kimura , Kenji Sano , Nobuo Nakazawa
发明人： Seiji Kimura , Kenji Sano , Nobuo Nakazawa
IPC分类号： G04G3/02 , G04C3/00 , G04B19/30 , G04C21/00
CPC分类号： G04G3/025
摘要： The present disclosure is directed to an electronic digital clock made up of electronic components without using a chain of counters. The digital clock utilizes shift registers with a recirculation path for storing the time information as to hours, minutes and/or seconds and a computing circuit for repeatedly adding the time information one by one in accordance with a predetermined clock base frequency.
摘要翻译：本公开涉及由电子组件构成的电子数字时钟，而不使用一连串的计数器。数字时钟利用具有用于存储关于小时，分钟和/或秒的时间信息的再循环路径的移位寄存器，以及用于根据预定时钟基频逐个地逐次添加时间信息的计算电路。

8. 发明授权

US4262352A Electronic multifunction timepiece employing the PLA system 失效
标题翻译：采用PLA系统的电子多功能钟表
公开(公告)号：US4262352A
公开(公告)日：1981-04-14
申请号：US13067
申请日：1979-02-21
申请人： Isamu Kobayashi , Takashi Ito
发明人： Isamu Kobayashi , Takashi Ito
IPC分类号： G04F10/00 , G04G3/02 , G04G13/00 , G04G99/00 , G04C19/00 , G04C15/00
CPC分类号： G04G99/006 , G04G13/00 , G04G3/025
摘要： Disclosed is an electronic multifunction timepiece employing the PLA system, including a key input circuit, a clock pulse generator circuit, a random access memory which stores time data therein, an adder circuit, and a read only memory which stores therein control instructions for controlling operations of said random access memory and said adder circuit and for causing said random access memory to write renewed time data and which provides the control signals sequentially on the basis of clock pulses of said clock pulse generator circuit, characterized in that said read only memory comprises a first read only memory which stores therein control signals for renewing the time data of said random access memory independently or operation modes appointed by said key input circuit, and a second read only memory which stores therein control instructions for controlling information processing operations in the operation modes appointed from said key input circuit.
摘要翻译：公开了一种采用PLA系统的电子多功能钟表，包括键输入电路，时钟脉冲发生器电路，存储时间数据的随机存取存储器，加法器电路和只读存储器，其中存储用于控制操作的控制指令的所述随机存取存储器和所述加法器电路，并且用于使所述随机存取存储器写入更新的时间数据，并且基于所述时钟脉冲发生器电路的时钟脉冲顺序提供控制信号，其特征在于，所述只读存储器包括：第一只读存储器，其中存储有用于更新所述随机存取存储器的时间数据的控制信号或由所述键输入电路指定的操作模式;以及第二只读存储器，其中存储用于控制操作模式中的信息处理操作的控制指令从所述键输入电路指定。

9. 发明授权

US4224531A Data transfer circuit 失效
标题翻译：数据传输电路
公开(公告)号：US4224531A
公开(公告)日：1980-09-23
申请号：US883867
申请日：1978-03-06
申请人： Heihachiro Ebihara , Fukuo Sekiya , Takashi Yamada
发明人： Heihachiro Ebihara , Fukuo Sekiya , Takashi Yamada
IPC分类号： G04G3/02 , G11C19/00 , G11C19/18 , G11C19/28
CPC分类号： G11C19/00 , G04G3/025 , G11C19/184
摘要： A data transfer circuit consisting of a shift register circuit, which is efficiently applicable to portable electronic devices such as a portable electronic timepiece, electronic computer or the like is disclosed. The circuit comprises a first shift register circuit and a second shift register circuit to which is transferred data from said first shift register circuit. The second shift register circuit includes at least first stage bit whose data transfer is controlled by two phase clocks and another bit whose data transfer is controlled by one phase clock.
摘要翻译：公开了一种数据传输电路，其包括可有效地应用于便携式电子钟表，电子计算机等便携式电子设备的移位寄存器电路。电路包括第一移位寄存器电路和第二移位寄存器电路，从第一移位寄存器电路传送数据。第二移位寄存器电路至少包括第一级位，其数据传输由两个相位时钟控制，另一位的数据传输由一个相位时钟控制。

10. 发明授权

US4132060A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4132060A
公开(公告)日：1979-01-02
申请号：US809710
申请日：1977-06-24
申请人： Toshio Kashio
发明人： Toshio Kashio
IPC分类号： G04G3/02 , G04B27/00
CPC分类号： G04G3/025
摘要： An electronic timepiece uses a dynamic type shift register, as a time count circuit, which has a plurality of memory sections corresponding to an equal number of time count units and a cycle number memory section arranged such that it is preceded by said plurality of memory sections. An adder and shift memory unit are serially connected to the shift register to provide a shift circulation circuit and the shift circulation is effected by an oscillation signal from a reference oscillator. The adder adds [1] to the contents of the cycle number memory section for each data shift cycle of the shift register. Each time the count value of the cycle number memory section reaches a predetermined cycle number, the count value of a smallest time unit is counted one step. In this way, a carry is propagated to the subsequent large time unit memory sections according to the data shift circulation cycle of the shift register. A memory circuit is also provided which preliminarily stores a correction value corresponding to an error occuring between the oscillation frequency of the reference oscillator as generated per unit time and the standard oscillation frequency which drives the shift circulation circuit. Upon receipt of a correction timing signal the memory circuit has its correction value substracted at a rate of one circulation cycle per minute, thereby to correct such an error. The correction value indicates a total number of subtractive circulation cycle per hour.
摘要翻译：电子钟表使用动态型移位寄存器作为时间计数电路，其具有对应于相等数量的时间计数单元的多个存储器部分和循环数存储器部分，其被布置成使得它在所述多个存储器部分之前。加法器和移位存储器单元串联连接到移位寄存器以提供移位循环电路，并且移位循环由来自参考振荡器的振荡信号来实现。对于移位寄存器的每个数据移位周期，加法器将[1]加到周期数存储器部分的内容。每当循环次数存储部分的计数值达到预定循环次数时，将最小时间单位的计数值计数一步。以这种方式，根据移位寄存器的数据移位循环周期，进位传播到随后的大时间单元存储器部分。还提供了一种存储电路，其预先存储对应于每单位时间产生的基准振荡器的振荡频率与驱动移位循环电路的标准振荡频率之间出现的误差的校正值。在接收到校正定时信号时，存储器电路的校正值以每分钟一个循环循环的速率减法，从而校正这种误差。校正值表示每小时减去循环循环的总数。

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