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1. 发明授权

US07605855B2 Dual sensitivity image sensor 有权
标题翻译：双灵敏度图像传感器
公开(公告)号：US07605855B2
公开(公告)日：2009-10-20
申请号：US11216172
申请日：2005-09-01
申请人： Yibing Michelle Wang , Sandor Barna
发明人： Yibing Michelle Wang , Sandor Barna
IPC分类号： H04N5/335 , H01L27/00 , H03K23/46
CPC分类号： H04N5/35563 , H04N5/3559 , H04N5/374
摘要： A system of taking images of different sensitivities at the same time uses both an image sensor, and an auxiliary part to the image sensor. The image sensor element can be a photogate, and the auxiliary part can be the floating diffusion associated with the photogate. Both the photogate and the floating diffusion accumulate charge. Both are sampled at different times. The floating diffusion provides a lower sensitivity amount of charge than the photogate itself. The system can have a photogate and floating diffusion in each pixel along with a select transistor, a reset transistor, and a follower transistor. All of this circuitry can be formed of CMOS for example. The system can also operate in a column/parallel mode, where each column of the photo sensor array can have a column signal processor which samples and holds the reset signal, the floating diffusion signal and the photogate signal.
摘要翻译：同时拍摄不同灵敏度的图像的系统使用图像传感器和图像传感器的辅助部件。图像传感器元件可以是光栅，并且辅助部件可以是与光栅相关联的浮动扩散。光栅和浮动扩散都积聚电荷。两者都在不同时间采样。浮动扩散提供比光栅本身更低的灵敏度的电荷。该系统可以与选择晶体管，复位晶体管和跟随器晶体管一起在每个像素中具有光栅和浮动扩散。例如，所有这种电路可以由CMOS形成。该系统还可以以列/并行模式工作，其中光传感器阵列的每列可以具有采样并保持复位信号，浮动扩散信号和光栅信号的列信号处理器。

2. 发明申请

US20070152137A1 Differential column readout scheme for CMOS APS pixels 有权
标题翻译： CMOS APS像素差分列读出方案
公开(公告)号：US20070152137A1
公开(公告)日：2007-07-05
申请号：US11637239
申请日：2006-12-12
申请人： Sandor Barna , Alex Krymski
发明人： Sandor Barna , Alex Krymski
IPC分类号： H01J40/14 , G01J1/44 , H03F3/08
CPC分类号： H04N5/361 , H03F3/08 , H04N5/3575 , H04N5/378
摘要： The present invention provides an improved column readout circuitry and method of operation which minimizes substrate and other common mode noise during a read out operation. The circuit improves the consistency of the pixel to pixel output of the pixel array and increases the dynamic range of the pixel output. This is accomplished by obtaining a differential readout of the reset signal and integrated charge signal from a desired pixel along with the reset signal and charge signal from a reference circuit. In this manner common mode noise can be minimized by a combination of signals from the desired and reference pixels in the sample and hold aspect of the column circuitry. In one exemplary embodiment of the invention, a 3T pixel arrangement is used. In another exemplary embodiment, a 4T arrangement is used. Additional exemplary embodiments provide differential column readout circuitry that can be used with any two signal sources.
摘要翻译：本发明提供一种改进的列读出电路和操作方法，其在读出操作期间使衬底和其它共模噪声最小化。该电路提高像素阵列的像素与像素输出的一致性，并增加像素输出的动态范围。这是通过从参考电路获得来自期望像素的复位信号和积分电荷信号的差分读出以及复位信号和电荷信号来实现的。以这种方式，可以通过来自列电路的采样和保持方面中的期望参考像素和参考像素的信号的组合来最小化共模噪声。在本发明的一个示例性实施例中，使用3T像素排列。在另一示例性实施例中，使用4T布置。附加的示例性实施例提供可与任何两个信号源一起使用的差分列读出电路。

3. 发明申请

US20060113461A1 Dark current reduction circuitry for CMOS active pixel sensors 有权
公开(公告)号：US20060113461A1
公开(公告)日：2006-06-01
申请号：US11327359
申请日：2006-01-09
申请人： Sandor Barna
发明人： Sandor Barna
IPC分类号： H01L27/00
CPC分类号： H04N5/374 , H04N5/363 , H04N5/3698
摘要： A row driver circuit is disclosed for supplying a reset voltage to a plurality of reset transistors of an active pixel sensor array while minimizing gate induced drain leakage (GIDL). The row driver circuit is configured to supply a high voltage level (e.g., Vdd or higher) to the reset transistors of the array during a reset operation. The row driver circuit is further configured to supply a low voltage level (e.g., a voltage level higher than ground) to the reset transistors of the array when the pixels are not being reset (e.g., during integration). The reduced potential difference realized between the respective gates of the reset transistors and the respective photodiodes of the pixels, when the pixels are not being reset, results in reduced GIDL.

4. 发明申请

US20050145777A1 Power savings with multiple readout circuits 有权
标题翻译：多个读出电路节能
公开(公告)号：US20050145777A1
公开(公告)日：2005-07-07
申请号：US10745611
申请日：2003-12-29
申请人： Sandor Barna , Guy Moffat
发明人： Sandor Barna , Guy Moffat
IPC分类号： H04N5/374 , H04N5/378 , H01L27/00
CPC分类号： H04N5/378 , H04N5/343 , H04N5/3454 , H04N5/347
摘要： An imager with a switch circuit located between, and connected to, the pixel array and associated readout chains. In one embodiment the switch is located within the column sample and hold circuitry; in another embodiment the switch is located between the column sample and hold circuitry and the readout chains. The switch circuit ensures that signals from the column sample and hold circuitry are directed to enabled readout chains, which allows selective enabling/disabling of readout chains. By disabling readout chains, the imager's power consumption is reduced.
摘要翻译：具有位于并连接到像素阵列和相关联的读出链之间的开关电路的成像器。在一个实施例中，开关位于列采样和保持电路内; 在另一个实施例中，开关位于列样本和保持电路和读出链之间。开关电路确保来自列采样和保持电路的信号被引导到使能的读出链，这允许选择性地启用/禁用读出链。通过禁用读数链，成像器的功耗降低。

5. 发明申请

US20050077549A1 Frame shutter pixel with an isolated storage node 有权
标题翻译：具有隔离存储节点的帧快门像素
公开(公告)号：US20050077549A1
公开(公告)日：2005-04-14
申请号：US10623533
申请日：2003-07-22
申请人： Eric Fossum , Sandor Barna
发明人： Eric Fossum , Sandor Barna
IPC分类号： H01L21/00 , H01L27/146 , H01L27/148 , H01L31/062 , H01L31/113 , H04N3/15 , H04N5/335
CPC分类号： H01L27/14601 , H01L27/14609 , H01L27/14623
摘要： A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.
摘要翻译：帧快门式设备提供存储节点所位于的分离井。存储节点也被遮光罩屏蔽，以防止光电转换。

6. 发明授权

US6043690A Bidirectional follower for driving a capacitive load 失效
标题翻译：用于驱动电容性负载的双向跟随器
公开(公告)号：US6043690A
公开(公告)日：2000-03-28
申请号：US38635
申请日：1998-03-10
申请人： Alexander Krymski , Sandor Barna , Barmak Mansoorian
发明人： Alexander Krymski , Sandor Barna , Barmak Mansoorian
IPC分类号： H03K17/687 , H03K3/00
CPC分类号： H03K17/6872
摘要： A bidirectional source follower system includes an N channel transistor and P channel transistor which conduct in opposite ways. The n channel transistor is connected to quickly source current, however is relatively inefficient at sinking current. In contrast, the P channel transistor can sink current very quickly but is bad at source current. The two devices are connected together in a way which allows advantageous features of both.
摘要翻译：双向源极跟随器系统包括以相反方式导通的N沟道晶体管和P沟道晶体管。 n沟道晶体管连接到快速电源电流，然而在沉降电流方面效率相对较低。相比之下，P沟道晶体管可以非常快地吸收电流，但在源极电流下不好。两个装置以允许两者的有利特征的方式连接在一起。

7. 发明申请

US20100002118A1 DUAL SENSITIVITY IMAGE SENSOR 有权
标题翻译：双灵敏度图像传感器
公开(公告)号：US20100002118A1
公开(公告)日：2010-01-07
申请号：US12557670
申请日：2009-09-11
申请人： Yibing (Michelle) Wang , Sandor Barna
发明人： Yibing (Michelle) Wang , Sandor Barna
IPC分类号： H04N5/335
CPC分类号： H04N5/35563 , H04N5/3559 , H04N5/374
摘要： A system of taking images of different sensitivities at the same time uses both an image sensor, and an auxiliary part to the image sensor. The image sensor element can be a photogate, and the auxiliary part can be the floating diffusion associated with the photogate. Both the photogate and the floating diffusion accumulate charge. Both are sampled at different times. The floating diffusion provides a lower sensitivity amount of charge than the photogate itself. The system can have a photogate and floating diffusion in each pixel along with a select transistor, a reset transistor, and a follower transistor. All of this circuitry can be formed of CMOS for example. The system can also operate in a column/parallel mode, where each column of the photo sensor array can have a column signal processor which samples and holds the reset signal, the floating diffusion signal and the photogate signal.
摘要翻译：同时拍摄不同灵敏度的图像的系统使用图像传感器和图像传感器的辅助部件。图像传感器元件可以是光栅，并且辅助部件可以是与光栅相关联的浮动扩散。光栅和浮动扩散都积聚电荷。两者都在不同时间采样。浮动扩散提供比光栅本身更低的灵敏度的电荷。该系统可以与选择晶体管，复位晶体管和跟随器晶体管一起在每个像素中具有光栅和浮动扩散。例如，所有这种电路可以由CMOS形成。该系统还可以以列/并行模式工作，其中光传感器阵列的每列可以具有采样并保持复位信号，浮动扩散信号和光栅信号的列信号处理器。

8. 发明申请

US20070030371A1 Frame shuttering scheme for increased frame rate 有权
标题翻译：用于增加帧速率的帧快门方案
公开(公告)号：US20070030371A1
公开(公告)日：2007-02-08
申请号：US11490523
申请日：2006-07-21
申请人： Sandor Barna , Eric Fossum
发明人： Sandor Barna , Eric Fossum
IPC分类号： H04N5/335
CPC分类号： H04N5/374 , H04N5/3452
摘要： Charge is integrated in N>=2 different groups within a frame buffer to form multiple image fields.
摘要翻译：电荷集成在帧缓冲器内的N> = 2个不同组中以形成多个图像场。

9. 发明授权

US06977603B1 Nonlinear flash analog to digital converter used in an active pixel system 有权
标题翻译：在有源像素系统中使用的非线性闪光模数转换器
公开(公告)号：US06977603B1
公开(公告)日：2005-12-20
申请号：US09711379
申请日：2000-11-09
申请人： Sandor Barna , Daniel Van Blerkom , Eric R. Fossum
发明人： Sandor Barna , Daniel Van Blerkom , Eric R. Fossum
IPC分类号： H03M1/36 , H04N5/335 , H03M1/12
CPC分类号： H03M1/367 , H04N5/378
摘要： A non-uniform resistor is used with a flash A to D converter in order to provide an A to D output which is not linear. The nonlinearity of the A to D output is specially designed to carry out a predetermined correction of the signal.
摘要翻译：闪光A到D转换器使用不均匀的电阻，以提供不是线性的A到D输出。 A到D输出的非线性特别设计用于执行信号的预定校正。

10. 发明申请

US20070090987A1 Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry 有权
标题翻译：在两级流水线ADC和/或两个通道的信号处理电路之间共享运算放大器
公开(公告)号：US20070090987A1
公开(公告)日：2007-04-26
申请号：US11604901
申请日：2006-11-28
申请人： Taehee Cho , Sandor Barna , Andrew Lever , Kwang-Bo Cho , Chiajen Lee
发明人： Taehee Cho , Sandor Barna , Andrew Lever , Kwang-Bo Cho , Chiajen Lee
IPC分类号： H03M1/38
CPC分类号： H03M1/0607 , H03M1/0695 , H03M1/1225 , H03M1/442
摘要： A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.
摘要翻译：在级/通道的放大器配置之前，在流水线模数转换器的两个级和/或两个信道处理电路之间共享的运算放大器的输入端放电寄生电容的机构被切换。当在两个时钟相位之间产生短暂的复位脉冲时，会发生放电动作。短复位脉冲施加到连接到运算放大器输入的开关。当复位脉冲闭合开关时，产生放电路径，运算放大器输入端的任何寄生电容通过路径放电。寄生电容的放电大大减轻了存储器效应和与存储器效应相关的问题。

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