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1. 发明申请

US20040071205A1 System and method of equalization of high speed signals 有权
标题翻译：高速信号均衡的系统和方法
公开(公告)号：US20040071205A1
公开(公告)日：2004-04-15
申请号：US10412101
申请日：2003-04-10
发明人： James Gorecki
IPC分类号： H03H007/30 , H03K005/159 , H03H007/40 , H04L027/20 , H03K009/02 , H03K007/02
CPC分类号： H04L25/03343 , H04L25/03038 , H04L25/03885
摘要： In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to introduce intersymbol interference in order to improve the signal integrity in high-speed communications and enhance the operation and performance of such systems. In this regard, the equalization circuitry includes temporally overlapping leading and/or trailing taps (relative to the data (symbol) signal) to reduce, minimize, mitigate or effectively eliminate pre-cursor and/or post-cursor intersymbol interference due to, for example, bandwidth limitations and reflections in high-speed digital communication systems. The amount of equalization may be programmed, adjusted or controlled by varying the positioning of the tap(s), varying the coefficients of the tap(s), and/or varying the pulse durations of the tap(s) (that is, the pulse duration of the equalization signal attributed to the tap).
摘要翻译：在一个方面，本发明涉及用于通过通信信道（例如背板）来增强高速数字通信的性能的技术和系统。在本发明的这个方面，发射机包括均衡电路，以补偿高速数字通信系统中的带宽限制和反射。在一个实施例中，均衡电路被设计，编程和/或配置为引入符号间干扰，以便改善高速通信中的信号完整性并增强这些系统的操作和性能。在这方面，均衡电路包括时间上重叠的前导和/或后退抽头（相对于数据（符号）信号）），以减少，最小化，减轻或有效地消除由于以下原因造成的前置和/或后标签符号间干扰例如，高速数字通信系统中的带宽限制和反射。可以通过改变水龙头的定位，改变水龙头的系数和/或改变水龙头的脉冲持续时间来编程，调节或控制均衡的量（即，归因于抽头的均衡信号的脉冲持续时间）。

2. 发明申请

US20040071204A1 System and method of equalization of high speed signals 有权
公开(公告)号：US20040071204A1
公开(公告)日：2004-04-15
申请号：US10410942
申请日：2003-04-10
发明人： James Gorecki
IPC分类号： H03H007/40 , H03H007/30 , H03K005/159 , H04L027/20 , H03K007/02 , H03K009/02
CPC分类号： H04L25/03343 , H04L25/03038 , H04L25/03885
摘要： In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to introduce intersymbol interference in order to improve the signal integrity in high-speed communications and enhance the operation and performance of such systems. In this regard, the equalization circuitry includes temporally overlapping leading and/or trailing taps (relative to the data (symbol) signal) to reduce, minimize, mitigate or effectively eliminate pre-cursor and/or post-cursor intersymbol interference due to, for example, bandwidth limitations and reflections in high-speed digital communication systems. The amount of equalization may be programmed, adjusted or controlled by varying the positioning of the tap(s), varying the coefficients of the tap(s), and/or varying the pulse durations of the tap(s) (that is, the pulse duration of the equalization signal attributed to the tap).

3. 发明申请

US20040062319A1 Pulse amplitude modulated system with reduced intersymbol interference 有权
标题翻译：具有减少符号间干扰的脉冲幅度调制系统
公开(公告)号：US20040062319A1
公开(公告)日：2004-04-01
申请号：US10261574
申请日：2002-10-01
申请人： Intel Corporation
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
IPC分类号： H04L025/34 , H04L025/49 , H03K007/02 , H03K009/02
CPC分类号： H04L25/4917
摘要： A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.
摘要翻译：提供了一种用于编码和接收数据的系统和方法。数据被编码为脉冲幅度调制信号，使得振幅信号不从最高信号电平转换到最低信号电平，并且不从最低信号电平转换到最高信号电平。在一些实施例中，通过查找表执行编码和解码，并且在另外的实施例中设计为使顺序脉冲幅度调制符号之间的步长最小化。

4. 发明申请

US20040141567A1 Multi-level pulse amplitude modulation receiver 有权
标题翻译：多级脉冲幅度调制接收机
公开(公告)号：US20040141567A1
公开(公告)日：2004-07-22
申请号：US10348877
申请日：2003-01-22
发明人： Fuji Yang , Michael L. Craner
IPC分类号： H04L025/34 , H04L025/49 , H03K007/02 , H03K009/02
CPC分类号： H04L25/069 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/033 , H04L25/066 , H04L25/4917
摘要： Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The phase detector outputs are combined (e.g., via weighted voting, weighted average, minimum error, and/or minimum variance) to determine an optimized phase estimate for the clock used to sample the data at all three data slicers. Another 4-PAM implementation similarly includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The mid-amplitude edge slicer and phase detector are used in combination with the VCO to generate a central phase while a multiple-tap delay line provides N phase variants before and after the central phase. Information from the non-mid-amplitude edge slicers and phase detectors is used to choose a phase from among the phase variants that best suits the other data slicers. In yet another implementation, a single edge slicer, single phase detector, and single VCO is used to generate a key clock which is used by the edge slicer to track the symbol timing. A clock generator provides a single optimized clock (that is offset from the key clock) that is used by the data slicers. Bit error rates from the data slicers are used to adjust the offset until the data slicer clock is optimized with respect to all the slicers. Alternatively, multiple clocks are generated via offsets from the key clock, each being optimized to the data slicer group that it drives.
摘要翻译：多级相位幅度（M-PAM）时钟和数据恢复电路使用来自多个相位检测器的信息来生成为每个数据限幅器优化的一个或多个数据采样时钟。一个可能的4-PAM实现包括3个数据限幅器，3个边缘限幅器，3个相位检测器和一个VCO。相位检测器输出被组合（例如，经由加权投票，加权平均，最小误差和/或最小方差）以确定用于在所有三个数据限幅器上采样数据的时钟的优化相位估计。另一个4-PAM实现类似地包括3个数据限幅器，3个边缘限幅器，3个相位检测器和一个VCO。中间幅度边缘限幅器和相位检测器与VCO组合使用以产生中心相位，而多抽头延迟线在中心相之前和之后提供N相变量。来自非中间幅度边缘限幅器和相位检测器的信息用于从最适合其他数据限幅器的相位变量中选择一个相位。在又一实现中，使用单个边缘限幅器，单相检测器和单个VCO来产生密钥时钟，该时钟由边缘限幅器用于跟踪符号定时。时钟发生器提供由数据限幅器使用的单个优化时钟（偏离关键时钟）。来自数据限幅器的位错误率用于调整偏移量，直到相对于所有切片器优化数据切片器时钟。或者，通过来自键时钟的偏移产生多个时钟，每个时钟被优化为其驱动的数据限幅器组。

5. 发明申请

US20030021340A1 Processing of quinary data 有权
标题翻译：处理数据
公开(公告)号：US20030021340A1
公开(公告)日：2003-01-30
申请号：US10196242
申请日：2002-07-17
发明人： Ciaran McElroy , Philip Curran , Alberto Molina Navarro
IPC分类号： H03H007/30 , H03H007/40 , H03K005/159 , H03K007/02 , H03K009/02
CPC分类号： G06F7/4824 , H03H17/0225
摘要： A FIR in a Gigabit transceiver represents data words in three bits: SIGN representing word sign, SHIFT representing requirement for a shift operation, and ZERO indicating whether the word is zero. An AND gate ANDs a multiplier and the ZERO bit, an XOR gate XORs the SIGN bit and the output of the AND gate, and a multiplier left-shifts the coefficient using the SHIFT bit and the output of the XOR gate. The circuit has a very low gate count.
摘要翻译：千兆收发器中的FIR表示三位数据字：SIGN表示字符号，SHIFT表示移位操作的要求，ZERO表示字是否为零。与门AND乘法器和零位，异或门将SIGN位和与门的输出异或，乘法器使用SHIFT位和XOR门的输出来左移系数。电路具有非常低的门数。

6. 发明申请

US20040008794A1 Method and apparatus for constellation shaping 有权
标题翻译：用于星座成形的方法和装置
公开(公告)号：US20040008794A1
公开(公告)日：2004-01-15
申请号：US10194741
申请日：2002-07-10
发明人： Brett Anthony McClellan
IPC分类号： H04K001/10 , H04L027/28 , H03K007/02 , H03K009/02
CPC分类号： H04L1/006 , H04L1/0071 , H04L25/4917
摘要： A method and apparatus is disclosed for facilitating high-speed data communication. In one embodiment a receiver is configured to include error correction coding in an interleaved environment to increase data transmission rates. In one embodiment the signal mapping scheme includes constellation shaping to reduce transmit power levels. In one embodiment 8-state Ungerboeck trellis coding is implemented with 4-dimensional PAM 10 signal mapping.
摘要翻译：公开了一种便于高速数据通信的方法和装置。在一个实施例中，接收机被配置为在交错环境中包括纠错编码以增加数据传输速率。在一个实施例中，信号映射方案包括星座整形以降低发射功率电平。在一个实施例中，使用4维PAM 10信号映射来实现8状态Ungerboeck格状编码。

7. 发明申请

US20030206578A1 Systems and methods for fractional bit rate encoding in a pulse amplitude modulation communication system 失效
$Systems and methods for fractional bit rate encoding in a pulse amplitude modulation communication system$
标题翻译：脉冲幅度调制通信系统中分数位速率编码的系统和方法
公开(公告)号：US20030206578A1
公开(公告)日：2003-11-06
申请号：US09785366
申请日：2001-02-16
发明人： William L. Betts
IPC分类号： H04B001/38 , H04L005/16 , H03K007/02 , H03K009/02
CPC分类号： H04L25/4908 , H04L25/4902
摘要： Systems and methods for encoding fractional bit rates in a pulse amplitude modulation (PAM) communication system are provided. The systems and methods enable a first PAM transceiver to specify to second PAM transceiver a desired fractional bit rate for transmitting data to the first PAM transceiver. In this manner, the systems and methods of the present invention for the first time enable a single standardized specification of a generalized transmitter that may be used to implement any type of fractional encoding or mapping.
摘要翻译：提供了用于编码脉冲幅度调制（PAM）通信系统中的分数比特率的系统和方法。所述系统和方法使得第一PAM收发器能够向第二PAM收发器指定用于将数据发送到第一PAM收发器的期望的分数比特率。以这种方式，本发明的系统和方法首次使得可以用于实现任何类型的分数编码或映射的通用发射机的单个标准化规范。

8. 发明申请

US20030194016A1 System and method for high speed digital signaling 有权
标题翻译：高速数字信号的系统和方法
公开(公告)号：US20030194016A1
公开(公告)日：2003-10-16
申请号：US10414951
申请日：2003-04-16
发明人： James Gorecki , John T. Stonick , Un-Ku Moon
IPC分类号： H03C005/00 , H04L027/02 , H03K007/02 , H03K009/02
CPC分类号： H04L25/4919
摘要： The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs adaptive or adjustable equalization circuitry and techniques in the transmitter and/or receiver to enhance the system performance of, for example, a system using the PAM-4 coding.
摘要翻译：本发明一般涉及通过通信信道提供高速数字通信的方法，装置和制品。在一个方面，本发明在发射机和/或接收机中使用自适应或可调均衡电路和技术来增强例如使用PAM-4编码的系统的系统性能。

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