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1. 发明授权

US11876659B2 Communication system using shape-shifted sinusoidal waveforms 有权
公开(公告)号：US11876659B2
公开(公告)日：2024-01-16
申请号：US17571243
申请日：2022-01-07
申请人： TeraWave, LLC
发明人： Torsten Schultze
IPC分类号： H04L27/26 , H04L25/03 , H04L27/20 , H04B14/06 , H04L27/38 , H04L5/00 , H04B1/7176 , H04L27/34 , H04L1/00 , H04L25/06 , H04L25/49 , H04L27/36 , H04L27/04
CPC分类号： H04L27/2614 , H04B1/7176 , H04B14/06 , H04L1/0045 , H04L5/0048 , H04L25/03834 , H04L25/069 , H04L25/4921 , H04L27/2017 , H04L27/2602 , H04L27/2618 , H04L27/2623 , H04L27/2627 , H04L27/345 , H04L27/3411 , H04L27/3494 , H04L27/36 , H04L27/366 , H04L27/389 , H04L27/04
摘要： A data communication method in which input digital data is received and encoded into an encoded waveform having zero crossings representative of the input digital data. The encoding includes generating the encoded waveform based upon a continuous piecewise function having sinusoidal components. The continuous piecewise function may be used in generating a plurality of symbol waveforms, each of which occupies a period of the encoded waveform and represents bits of the input digital data. The plurality of symbol waveforms are defined so that a value of a phase offset used in the continuous piecewise function is different for each of the plurality of symbol waveforms, thereby resulting in each symbol waveform having a different zero crossing. An encoded analog waveform is generated from a representation of the encoded waveform and transmitted to a receiver.

2. 发明公开

US20230275792A1 TIMER-BASED EDGE-BOOSTING EQUALIZER FOR HIGH-SPEED WIRELINE TRANSMITTERS 审中-公开
公开(公告)号：US20230275792A1
公开(公告)日：2023-08-31
申请号：US17579405
申请日：2022-01-19
申请人： QUALCOMM Incorporated
发明人： Darius VALAEE , Patrick ISAKANIAN , Srivatsan THIRUVENGADAM
IPC分类号： H04L27/01 , H04L25/03 , H04L25/06
CPC分类号： H04L27/01 , H04L25/069 , H04L25/03343
摘要： An equalizing transmitter coupled to a serial transmission line has a driver circuit coupled between an input signal and the serial transmission line, the driver circuit being configured to receive power at a first voltage level. The equalizing transmitter has one or more helper circuits, each helper circuit being configured to receive a control signal and to pull the serial transmission line to a second voltage level when a pulse is present in the control signal. The second voltage level may be greater than the first voltage level. The equalizing transmitter has one or more pulse generation circuits, each pulse generation circuit being configured to receive the input signal and a delayed version of the input signal and to provide the pulse in the control signal when a difference in voltage state is detected between the input signal and the delayed version of the input signal.

3. 发明申请

US20180248723A1 Adaptive Equalization Using Correlation of Edge Samples with Data Patterns 审中-公开
公开(公告)号：US20180248723A1
公开(公告)日：2018-08-30
申请号：US15889273
申请日：2018-02-06
申请人： Rambus Inc.
发明人： Robert E. Palmer
IPC分类号： H04L27/01 , H04L25/03 , H04L25/06
CPC分类号： H04L27/01 , H04L7/041 , H04L7/046 , H04L25/03006 , H04L25/03273 , H04L25/069
摘要： An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

4. 发明授权

US09973220B2 Isolation circuits for digital communications and methods to provide isolation for digital communications 有权
公开(公告)号：US09973220B2
公开(公告)日：2018-05-15
申请号：US15166426
申请日：2016-05-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Bradley Allen Kramer , Mark W. Morgan , Swaminathan Sankaran
IPC分类号： H04L25/03 , H04B1/04 , H04L25/02 , H04L25/06 , H04L25/49
CPC分类号： H04B1/0475 , H01L2224/48091 , H03F1/02 , H03F3/24 , H04B2001/0408 , H04B2001/045 , H04L25/0266 , H04L25/069 , H04L25/49 , H01L2924/00014
摘要： Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes an isolation barrier, a burst encoder in a first circuit, and an edge pattern detector in a second circuit. The example isolation barrier electrically isolates the first circuit from the second circuit. The example burst encoder generates a first pattern in response to receiving a rising edge on an input signal and generates a second pattern in response to receiving a falling edge on the input signal. The example edge pattern detector detects the first pattern or the second pattern received from the burst encoder via the isolation barrier, sets an output signal at a first signal level in response to detecting the first pattern, and sets the output signal at a second signal level in response to detecting the second pattern.

5. 发明申请

US20160277048A1 Isolation Circuits for Digital Communications and Methods to Provide Isolation for Digital Communications 审中-公开
标题翻译：数字通信隔离电路和数字通信隔离方法
公开(公告)号：US20160277048A1
公开(公告)日：2016-09-22
申请号：US15166426
申请日：2016-05-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Bradley Allen Kramer , Mark W. Morgan , Swaminathan Sankaran
IPC分类号： H04B1/04 , H04L25/49
CPC分类号： H04B1/0475 , H01L2224/48091 , H03F1/02 , H03F3/24 , H04B2001/0408 , H04B2001/045 , H04L25/0266 , H04L25/069 , H04L25/49 , H01L2924/00014
摘要： Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes an isolation barrier, a burst encoder in a first circuit, and an edge pattern detector in a second circuit. The example isolation barrier electrically isolates the first circuit from the second circuit. The example burst encoder generates a first pattern in response to receiving a rising edge on an input signal and generates a second pattern in response to receiving a falling edge on the input signal. The example edge pattern detector detects the first pattern or the second pattern received from the burst encoder via the isolation barrier, sets an output signal at a first signal level in response to detecting the first pattern, and sets the output signal at a second signal level in response to detecting the second pattern.
摘要翻译：公开了用于数字通信的隔离电路和用于提供用于数字通信的隔离的方法。示例性隔离电路包括隔离栅，第一电路中的突发编码器和第二电路中的边缘图案检测器。示例性隔离屏障将第一电路与第二电路电隔离。响应于在输入信号上接收上升沿，示例性突发编码器产生第一模式，并且响应于在输入信号上接收到下降沿而产生第二模式。示例性边缘模式检测器经由隔离屏障检测从脉冲串编码器接收的第一模式或第二模式，响应于检测到第一模式而将输出信号设置在第一信号电平，并将输出信号设置在第二信号电平响应于检测到第二图案。

6. 发明申请

US20160254926A1 SUBSCRIBER STATION FOR A BUS SYSTEM AND METHOD FOR IMPROVING THE QUALITY OF RECEPTION IN A BUS SYSTEM 审中-公开
标题翻译：用于总线系统的订户站和用于提高总线系统中接收质量的方法
公开(公告)号：US20160254926A1
公开(公告)日：2016-09-01
申请号：US15032292
申请日：2014-10-20
申请人： ROBERT BOSCH GMBH
发明人： Steffen Walker , Bernd Hilgenberg
IPC分类号： H04L12/413 , H04B1/16
CPC分类号： H04L12/4135 , H04B1/16 , H04L25/0286 , H04L25/029 , H04L25/061 , H04L25/069 , H04L2012/40215
摘要： A subscriber station for a bus system and a method for improving the reception quality in the bus system are provided. The subscriber station includes an acquisition device for acquiring a bus state of a bus of the bus system, and a symmetrization device for the symmetrization, on the basis of the result of the acquisition device, of the bit durations and/or of the delay time durations of the rising and falling edge of a bit of signals received from the bus.
摘要翻译：提供一种用于总线系统的用户站和用于提高总线系统中的接收质量的方法。用户站包括用于获取总线系统的总线的总线状态的获取装置，以及用于基于获取装置的结果对比特征的比特持续时间和/或延迟时间的对称化装置从总线接收的一点信号的上升沿和下降沿的持续时间。

7. 发明授权

US08175192B2 Method and system for determining and removing DC offset in communication signals 失效
标题翻译：用于确定和消除通信信号中DC偏移的方法和系统
公开(公告)号：US08175192B2
公开(公告)日：2012-05-08
申请号：US11732339
申请日：2007-04-02
申请人： Steven D. Hall
发明人： Steven D. Hall
IPC分类号： H04L25/06 , H04L27/00
CPC分类号： H04L25/06 , H04L25/069
摘要： According to one exemplary embodiment, a method and system for determining and removing DC offset in an AC signal includes receiving an AC signal having a first-channel and a second-channel, e.g. an I-channel and a Q-channel, receiving a plurality of first-channel and second-channel samples, storing a negative first-channel sample corresponding to a first sign change in the plurality of second-channel samples, and storing a positive first-channel sample corresponding to a second sign change in the plurality of second-channel samples. The method further includes determining an average value of the negative first-channel sample and the positive first-channel sample, where the average value is the DC offset in the first-channel. The method can further include subtracting the determined DC offset from samples received in the first-channel (or the second-channel) prior to demodulation. The method and system can be implemented in, for example, a Bluetooth receiver.
摘要翻译：根据一个示例性实施例，用于确定和去除AC信号中的DC偏移的方法和系统包括接收具有第一信道和第二信道的AC信号，例如， I信道和Q信道，接收多个第一信道和第二信道样本，将对应于第一符号变化的负第一信道样本存储在多个第二信道样本中，并且存储正的第一信道和第二信道样本对应于多个第二通道样本中的第二符号变化的通道样本。该方法还包括确定负第一通道采样和正的第一通道采样的平均值，其中平均值是第一通道中的直流偏移。该方法还可以包括在解调之前从在第一信道（或第二信道）中接收的样本中减去确定的DC偏移。该方法和系统可以在例如蓝牙接收器中实现。

8. 发明申请

US20120027129A1 DEMODULATION CIRCUIT, DIGITAL MICROWAVE SYSTEM AND DEMODULATION METHOD 有权
标题翻译：解调电路，数字微波系统和解调方法
公开(公告)号：US20120027129A1
公开(公告)日：2012-02-02
申请号：US13270108
申请日：2011-10-10
申请人： Guixue ZHAO , Tianxiang WANG
发明人： Guixue ZHAO , Tianxiang WANG
IPC分类号： H04B1/10 , H03D1/24 , H03K9/06 , H04L27/14 , H03K9/00 , H03K9/02 , H04L27/06 , H03D3/00
CPC分类号： H04L27/06 , H04L25/069 , H04L27/1563
摘要： A demodulation circuit, a digital microwave system including the demodulation circuit, and a signal demodulation method are provided. The demodulation circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit connected in turn. The fourth circuit includes a pulse counting unit and a data decision unit connected in turn. The signal demodulation method includes: performing bandpass filtering on input signals; increasing gains of the bandpass filtered signals; extracting pulse signals are extracted from the gain-increased signals; counting the extracted pulse signals; filtering the pulse signals having counting values falling outside of a predetermined range, and outputting the filtered pulse signals.
摘要翻译：提供了解调电路，包括解调电路的数字微波系统和信号解调方法。解调电路包括依次连接的第一电路，第二电路，第三电路和第四电路。第四电路包括依次连接的脉冲计数单元和数据判定单元。信号解调方法包括：对输入信号进行带通滤波; 增加带通滤波信号的增益; 从增益增益信号中提取提取脉冲信号; 对所提取的脉冲信号进行计数; 对具有落在预定范围之外的计数值的脉冲信号进行滤波，并输出经滤波的脉冲信号。

9. 发明申请

US20120020399A1 RECEIVER CIRCUIT 有权
标题翻译：接收电路
公开(公告)号：US20120020399A1
公开(公告)日：2012-01-26
申请号：US13155485
申请日：2011-06-08
申请人： Yoshiyasu DOI
发明人： Yoshiyasu DOI
IPC分类号： H04B1/10
CPC分类号： H04L7/0331 , H04L25/069
摘要： A receiver circuit includes: a first sampling circuit to sample input data in synchronization with a first edge of a sampling clock signal; a second sampling circuit to sample the input data in synchronization with a second edge of the sampling clock signal; a duty-cycle-distortion detection circuit to detect a duty-cycle-distortion amount indicating an error in a duty ratio of the sampling clock signal based on first data which is sampled by the first sampling circuit and second data which is sampled by the second sampling circuit; a correction circuit to correct the first data or the second data to generate first corrected data or second corrected data, respectively, based on the duty-cycle-distortion amount; and a clock data recovery circuit to select data out of the first corrected data and the second data and to recover the selected data.
摘要翻译：接收机电路包括：第一采样电路，用于与采样时钟信号的第一边沿同步地采样输入数据; 第二采样电路，用于与采样时钟信号的第二边沿同步地采样输入数据; 占空比失真检测电路，用于基于由第一采样电路采样的第一数据和由第二采样电路采样的第二数据来检测指示采样时钟信号的占空比误差的占空比失真量; 采样电路; 校正电路，用于校正第一数据或第二数据，以分别基于占空比失真量产生第一校正数据或第二校正数据; 以及时钟数据恢复电路，用于从第一校正数据和第二数据中选择数据，并恢复所选择的数据。

10. 发明申请

US20110150136A1 DUTY CYCLE COMPENSATING DIGITAL DATA RECEIVER 审中-公开
标题翻译：占空比数字数据接收器
公开(公告)号：US20110150136A1
公开(公告)日：2011-06-23
申请号：US12643532
申请日：2009-12-21
申请人： Roger A. Bethard
发明人： Roger A. Bethard
IPC分类号： H04L27/00
CPC分类号： H04L25/069 , H04L7/0331
摘要： A data communication receiver includes an interface operable to receive at least one incoming data signal. A transition point tracker is operable to track data transition points of the data signal, and a data sampler is operable to sample the data signal at a desired sampling point between transition points.
摘要翻译：数据通信接收机包括可操作以接收至少一个输入数据信号的接口。转换点跟踪器可操作以跟踪数据信号的数据转换点，并且数据采样器可操作以在转换点之间的期望采样点对数据信号进行采样。

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