专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20030184274A1 CURRENT MIRROR CIRCUITS 有权
标题翻译：当前镜像电路
公开(公告)号：US20030184274A1
公开(公告)日：2003-10-02
申请号：US10106757
申请日：2002-03-26
申请人： Intel Corporation
发明人： David J. Comer , Aaron K. Martin , James E. Jaussi
IPC分类号： G05F003/16
CPC分类号： G05F3/262
摘要： A current mirror includes an input node to receive an input current, an output node to produce an output current, and a reference node. The current mirror also includes a potential reduction unit to allow the voltage at the input node to be less than the voltage at the reference node.
摘要翻译：电流镜包括用于接收输入电流的输入节点，产生输出电流的输出节点和参考节点。电流镜还包括允许输入节点处的电压小于参考节点处的电压的电位减小单元。

2. 发明申请

US20030187903A1 Multiplier using MOS channel widths for code weighting 失效
标题翻译：乘法器使用MOS通道宽度进行代码加权
公开(公告)号：US20030187903A1
公开(公告)日：2003-10-02
申请号：US10106736
申请日：2002-03-26
申请人： Intel Corporation
发明人： David J. Comer , Aaron K. Martin , James E. Jaussi
IPC分类号： G06F007/50
CPC分类号： G06G7/16
摘要： A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.
摘要翻译：乘法器包括用于接收输入信号以在多个源节点处提供电流的输入级。输出级包括多个晶体管组，每个晶体管组具有多个二进制加权晶体管对。选择单元基于二进制码信号来选择二进制加权晶体管对，使得每个晶体管对将来自源节点之一的电流传递到参考节点或求和节点。

3. 发明申请

US20030184338A1 Multiplier with output current scaling 失效
标题翻译：输出电流缩放倍数
公开(公告)号：US20030184338A1
公开(公告)日：2003-10-02
申请号：US10106617
申请日：2002-03-26
申请人： Intel Corporation
发明人： David J. Comer , Aaron K. Martin , James E. Jaussi
IPC分类号： G06F007/38
CPC分类号： G06G7/16
摘要： A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of currents produced by the output stage can be controlled by selecting appropriate parameters of the transistor pairs.
摘要翻译：乘法器包括用于接收输入信号以在多个源节点处提供电流的输入级。输出级包括多个晶体管组，每个晶体管组包括多个晶体管对。可以通过选择晶体管对的适当参数来控制由输出级产生的电流值。

4. 发明申请

US20030067325A1 CURRENT MODE BIDIRECTIONAL PORT WITH DATA CHANNEL USED FOR SYNCHRONIZATION 有权
标题翻译：具有用于同步的数据通道的电流模式双向端口
公开(公告)号：US20030067325A1
公开(公告)日：2003-04-10
申请号：US09972327
申请日：2001-10-05
申请人： Intel Corporation
发明人： Matthew B. Haycock , Stephen R. Mooney , Aaron K. Martin
IPC分类号： H03K019/0175
CPC分类号： H04L25/45 , H03K19/018592 , H04L7/0004
摘要： A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a data transceiver circuit. The combination data and synchronization transceiver circuit synchronizes the port with another simultaneous bidirectional port coupled to the same bus. The combination data and synchronization transceiver circuit includes a driver with a variable output current and a variable output resistance. Prior to synchronization, the driver has a low output current and low output resistance. When the simultaneous bidirectional port is ready to communicate, the variable output resistance is increased. When both simultaneous bidirectional ports are ready, the variable output resistance is set to properly terminate the line, and the variable output current is set to provide a desired voltage swing.
摘要翻译：耦合到总线的同时双向端口组合同步电路和数据收发器电路。组合数据和同步收发器电路将端口与耦合到同一总线的另一个同时双向端口同步。组合数据和同步收发器电路包括具有可变输出电流和可变输出电阻的驱动器。在同步之前，驱动器具有低输出电流和低输出电阻。当同时双向端口准备通信时，可变输出电阻增加。当两个同时双向端口准备就绪时，可变输出电阻被设置为适当地终止线路，并且可变输出电流被设置为提供期望的电压摆幅。

5. 发明申请

US20030188234A1 Method and unit for deskewing signals 有权
标题翻译：消隐信号的方法和单元
公开(公告)号：US20030188234A1
公开(公告)日：2003-10-02
申请号：US10106636
申请日：2002-03-26
申请人： Intel Corporation
发明人： Bryan K. Casper , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock
IPC分类号： G11B005/00 , G06K005/04 , G11B020/20
CPC分类号： G11B20/1403 , G11B20/20 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0037
摘要： A clock deskew method includes receiving a data signal and a clock signal, processing the data signal to generate a jitter characterization parameter, shifting the clock signal by about 90null from the jitter characterization parameter to generate a sampling clock signal, and sampling the data signal with the sampling clock signal to generate a deskewed data signal. A clock deskew unit includes a clock unit, a sampling unit, and a deskew unit. The deskew unit includes a jitter characterization unit that generates a jitter characterization parameter. The jitter characterization parameter establishes a phase location for aligning a clock signal. Shifting the clock signal by about 90null from the phase location of the jitter characterization parameter provides a location for sampling a data signal to generate a deskewed data signal.
摘要翻译：时钟偏移校正方法包括接收数据信号和时钟信号，处理数据信号以产生抖动表征参数，将时钟信号从抖动表征参数移位约90°以产生采样时钟信号，并对数据信号进行采样采样时钟信号产生一个偏斜数据信号。时钟解调单元包括时钟单元，采样单元和歪斜校正单元。去偏转单元包括产生抖动表征参数的抖动表征单元。抖动特征参数建立一个相位位置，用于对准时钟信号。将时钟信号从抖动特征参数的相位位置移位大约90°，提供了一个用于采样数据信号以产生偏斜数据信号的位置。

6. 发明申请

US20030145162A1 Memory pass-band signaling 有权
标题翻译：存储器通带信令
公开(公告)号：US20030145162A1
公开(公告)日：2003-07-31
申请号：US10062034
申请日：2002-01-31
申请人： Intel Corporation
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
IPC分类号： G06F012/00 , G06F012/14
CPC分类号： G06F12/06
摘要： A memory system provides includes multiple memory devices or banks of memory devices that are assigned frequency pass-bands. Each memory device includes frequency translation circuitry to up-convert and down-convert data signals to and from the assigned frequency pass-band. Some embodiments include simultaneous bidirectional communications between memory devices and a controller by assigning multiple frequency pass-bands to each memory device or bank of memory devices. A memory system substrate is provided with bandpass filters between memory device footprints and other device footprints.
摘要翻译：存储器系统提供包括分配频率通带的多个存储器件或存储器器件组。每个存储器件包括频率转换电路，用于将数据信号上变频和下转换到分配的频率通带。一些实施例包括通过将多个频率通带分配给每个存储器件或存储器组来同时在存储器件与控制器之间进行双向通信。存储器系统基板在存储器件占用面积和其他器件占用面积之间提供带通滤波器。

7. 发明申请

US20030122586A1 Differential cascode current mode driver 有权
公开(公告)号：US20030122586A1
公开(公告)日：2003-07-03
申请号：US10368901
申请日：2003-02-14
申请人： Intel Corporation
发明人： Aaron K. Martin , Stephen R. Mooney
IPC分类号： H03K019/094
CPC分类号： H04L25/0282 , H03K19/01721 , H03K19/018528 , H04L25/0272 , H04L25/0294
摘要： A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

8. 发明申请

US20030112644A1 Voltage multiplier circuit 失效
标题翻译：电压倍增电路
公开(公告)号：US20030112644A1
公开(公告)日：2003-06-19
申请号：US10021864
申请日：2001-12-17
申请人： Intel Corporation
发明人： Aaron K. Martin , David J. Comer
IPC分类号： H02M003/18
CPC分类号： G05F1/561 , G06J1/00 , H03G1/0088 , H03G3/001
摘要： A voltage multiplier circuit includes a voltage-to-current converter, a current multiplier, and load devices. The voltage-to-current converter receives a differential input voltage, and produces a differential current. The differential current is received by the current multiplier, which produces a scaled output current. The amount of scaling is provided by a digital control word. Load devices produce a differential output voltage from the scaled output current. Multiple voltage-to-current converters and current multipliers can be coupled in parallel so that the scaled output currents sum.
摘要翻译：电压倍增器电路包括电压 - 电流转换器，电流倍增器和负载装置。电压 - 电流转换器接收差分输入电压，并产生差分电流。差分电流由电流乘法器接收，产生一个缩放的输出电流。缩放量由数字控制字提供。负载设备从缩放的输出电流产生差分输出电压。多个电压 - 电流转换器和电流乘法器可以并联耦合，以便缩放的输出电流相加。

9. 发明申请

US20040267469A1 On-die waveform capture 审中-公开
标题翻译：片上波形捕获
公开(公告)号：US20040267469A1
公开(公告)日：2004-12-30
申请号：US10603374
申请日：2003-06-25
申请人： Intel Corporation
发明人： Bryan K. Casper , Aaron K. Martin , James E. Jaussi , Stephen R. Mooney
IPC分类号： G06F019/00
CPC分类号： G01R31/318541 , G01R31/31708
摘要： A port circuit includes circuitry to capture a waveform. The port circuit may be a unidirectional port circuit, or a bidirectional port circuit.

10. 发明申请

US20040062319A1 Pulse amplitude modulated system with reduced intersymbol interference 有权
标题翻译：具有减少符号间干扰的脉冲幅度调制系统
公开(公告)号：US20040062319A1
公开(公告)日：2004-04-01
申请号：US10261574
申请日：2002-10-01
申请人： Intel Corporation
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
IPC分类号： H04L025/34 , H04L025/49 , H03K007/02 , H03K009/02
CPC分类号： H04L25/4917
摘要： A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.
摘要翻译：提供了一种用于编码和接收数据的系统和方法。数据被编码为脉冲幅度调制信号，使得振幅信号不从最高信号电平转换到最低信号电平，并且不从最低信号电平转换到最高信号电平。在一些实施例中，通过查找表执行编码和解码，并且在另外的实施例中设计为使顺序脉冲幅度调制符号之间的步长最小化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式