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1. 发明授权

US5893743A Process of fabricating semiconductor device 失效
标题翻译：制造半导体器件的工艺
公开(公告)号：US5893743A
公开(公告)日：1999-04-13
申请号：US877422
申请日：1997-06-17
申请人： Takayuki Gomi , Hiroaki Ammo
发明人： Takayuki Gomi , Hiroaki Ammo
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/732
CPC分类号： H01L21/82285
摘要： A process for forming a first bipolar transistor having a single polysilicon structure and a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor on the same substrate. In the process of fabricating a semiconductor device in which a first bipolar transistor having a single polysilicon structure, a second bipolar transistor having a single polysilicon structure and being of a conducting type opposite to that of the first bipolar transistor, and a third bipolar transistor having a double polysilicon structure are provided on the same semiconductor substrate, a base contact portion of the first bipolar transistor and an emitter of the second bipolar transistor are formed in the same step, and an emitter of the first bipolar transistor and base contact portions of the second and third bipolar transistors are formed in the same step.
摘要翻译：一种用于形成具有单个多晶硅结构的第一双极晶体管和具有单个多晶硅结构并且在同一衬底上具有与第一双极晶体管相反的导电类型的第二双极晶体管的工艺。在制造其中具有单个多晶硅结构的第一双极晶体管，具有单个多晶硅结构并且具有与第一双极晶体管相反的导电类型的第二双极晶体管的半导体器件的过程中，以及第三双极晶体管，在相同的半导体衬底上设置双重多晶硅结构，第一双极晶体管的基极接触部分和第二双极晶体管的发射极在同一步骤中形成，并且第一双极晶体管和基极接触部分的发射极在同一步骤中形成第二和第三双极晶体管。

2. 发明授权

US5783472A Method of making an SOI transistor 失效
标题翻译：制造SOI晶体管的方法
公开(公告)号：US5783472A
公开(公告)日：1998-07-21
申请号：US787797
申请日：1997-01-23
申请人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
发明人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
IPC分类号： H01L29/73 , H01L21/22 , H01L21/331 , H01L21/38
CPC分类号： H01L29/7317 , H01L29/66265
摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.
摘要翻译：公开了能够形成窄尺寸扩散区域（例如基底宽度）的横向双极晶体管。晶体管在扩散区域的宽度方向上没有散射。通过在半导体部分中以大致均匀的浓度改变杂质扩散源并通过从杂质扩散源的扩散形成扩散区来减小发射极电阻。双极晶体管具有SOI结构。还公开了制造这种装置的方法。

3. 发明授权

US5643806A Manufacturing method for making bipolar device 失效
标题翻译：制造双极器件的方法
公开(公告)号：US5643806A
公开(公告)日：1997-07-01
申请号：US472869
申请日：1995-06-07
申请人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
发明人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
IPC分类号： H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/7322 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
摘要翻译：一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

4. 发明授权

US5541124A Method for making bipolar transistor having double polysilicon structure 失效
标题翻译：制造具有双重多晶硅结构的双极晶体管的方法
公开(公告)号：US5541124A
公开(公告)日：1996-07-30
申请号：US477471
申请日：1995-06-07
申请人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
发明人： Hiroyuki Miwa , Shigeru Kanematsu , Takayuki Gomi , Hiroaki Anmo , Takashi Noguchi , Katsuyuki Kato , Hirokazu Ejiri , Norikazu Ouchi
IPC分类号： H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/7322 , H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.
摘要翻译：一种半导体器件及其制造方法，其可以通过减小基极宽度同时实现基极通过时间的减少，并且通过降低基极电阻降低基极电阻。半导体器件通过包括以下步骤的方法制造：在半导体衬底中形成第一导电类型的第一杂质扩散层; 形成连接到第一杂质扩散层的导电膜; 在导电膜上形成第一绝缘膜; 通过由第一绝缘膜和导电膜构成的层压膜形成第一孔; 在暴露于第一孔的半导体衬底中形成第一导电类型的第二杂质扩散层; 从所述第一孔中的第二绝缘膜形成侧壁以形成第二孔; 以及在暴露于第二孔的半导体衬底中形成第一导电类型的第三杂质扩散层。

5. 发明授权

US6034402A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US6034402A
公开(公告)日：2000-03-07
申请号：US95043
申请日：1998-06-10
申请人： Hiroaki Ammo , Takayuki Gomi
发明人： Hiroaki Ammo , Takayuki Gomi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L29/76
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A semiconductor device comprises: a substrate; a first buried layer of a first conduction type formed in the substrate; a second buried layer of the first conduction type formed in the substrate; a third buried layer of the first conduction type formed in the substrate; an epitaxial layer of the first conduction type formed on the substrate; a well region of a second conduction type formed in the epitaxial layer above the third buried layer; source/drain regions of the first conduction type formed in the well region; a first base region of the second conduction type formed in the epitaxial layer above the first buried layer; a first impurity region of the first conduction type formed on the first base region; a second base region of the second conduction type formed in the epitaxial layer above the second buried layer; a second impurity region of the first conduction type formed on the second base region; a first lead-out layer of the first conduction type connected to the first buried layer; and a second lead-out layer of the first conduction type connected to the second buried layer. The second buried layer has an impurity concentration substantially equal to that of the third buried layer.
摘要翻译：半导体器件包括：衬底; 形成在基板中的第一导电类型的第一掩埋层; 形成在基板中的第一导电类型的第二掩埋层; 在衬底中形成第一导电类型的第三掩埋层; 在基板上形成第一导电类型的外延层; 形成在第三掩埋层上方的外延层中的第二导电类型的阱区; 在该区域中形成的第一导电类型的源极/漏极区域; 形成在第一掩埋层上方的外延层中的第二导电类型的第一基极区; 形成在第一基极区上的第一导电类型的第一杂质区; 在第二掩埋层上方的外延层中形成的第二导电类型的第二基极区; 形成在第二基极区上的第一导电类型的第二杂质区; 连接到第一掩埋层的第一导电类型的第一引出层; 以及连接到第二掩埋层的第一导电类型的第二引出层。第二掩埋层的杂质浓度基本上等于第三掩埋层的杂质浓度。

6. 发明授权

US06008524A Integrated injection logic semiconductor device 失效
标题翻译：集成注入逻辑半导体器件
公开(公告)号：US06008524A
公开(公告)日：1999-12-28
申请号：US647771
申请日：1996-05-15
申请人： Takayuki Gomi
发明人： Takayuki Gomi
IPC分类号： H01L27/082 , H01L21/8226 , H01L27/02 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L27/0233
摘要： A logic circuit is formed of an I.sup.2 L cell structure in which a difference of switching speeds at every collector in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constant current source transistor and a switch transistor is formed on a common semiconductor substrate, a first semiconductor layer (13) doped with a first conductivity type impurity and a second semiconductor layer (19) doped with a second conductivity impurity are electrically isolated from each other on a semiconductor substrate. A plurality of collector electrodes of the switch transistor and a plurality of collector regions (20) based on diffusion of impurity are formed by the second semiconductor layer (19). The first semiconductor layer (13) includes a base electrode deriving portion, and a direct contact portion which directly contacts with the semiconductor substrate between a plurality of collector regions (20). An external base region (17) is formed by diffusion of first conductivity type impurity from the direct contact portion.
摘要翻译：逻辑电路由多集电极结构中的每个集电极的开关速度差小的I2L单元结构形成。在公共半导体衬底上形成有包括恒流源晶体管和开关晶体管的集成注入逻辑单元的半导体器件中，掺杂有第一导电型杂质的第一半导体层（13）和第二半导体层（19 ）掺杂有第二导电杂质在半导体衬底上彼此电隔离。由第二半导体层（19）形成开关晶体管的多个集电极和基于杂质扩散的多个集电极区域（20）。第一半导体层（13）包括基极导出部分和在多个集电极区域（20）之间与半导体衬底直接接触的直接接触部分。通过从直接接触部分扩散第一导电型杂质形成外部基极区（17）。

7. 发明授权

US5629217A Method and apparatus for SOI transistor 失效
标题翻译： SOI晶体管的方法和装置
公开(公告)号：US5629217A
公开(公告)日：1997-05-13
申请号：US319150
申请日：1994-10-06
申请人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
发明人： Hiroyuki Miwa , Takayuki Gomi , Katsuyuki Kato
IPC分类号： H01L29/73 , H01L21/22 , H01L21/331 , H01L21/38 , H01L21/26 , H01L21/265 , H01L21/306 , H01L21/479
CPC分类号： H01L29/7317 , H01L29/66265
摘要： A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.
摘要翻译：公开了能够形成窄尺寸扩散区域（例如基底宽度）的横向双极晶体管。晶体管在扩散区域的宽度方向上没有散射。通过在半导体部分中以大致均匀的浓度改变杂质扩散源并通过从杂质扩散源的扩散形成扩散区来减小发射极电阻。双极晶体管具有SOI结构。还公开了制造这种装置的方法。

8. 发明授权

US5414291A Semiconductor device and process for fabricating the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5414291A
公开(公告)日：1995-05-09
申请号：US189191
申请日：1994-01-31
申请人： Hiroyuki Miwa , Mamoru Shinohara , Takayuki Gomi , Tomotaka Fujisawa
发明人： Hiroyuki Miwa , Mamoru Shinohara , Takayuki Gomi , Tomotaka Fujisawa
IPC分类号： H01L27/06 , H01L27/02 , H01G4/06
CPC分类号： H01L27/0623
摘要： A semiconductor device comprising a MIS structure comprising a first electrically conductive film formed on an oxide film, a second electrically conductive film formed on at least a part of said first electrically conductive film, an insulator film formed on said second electrically conductive film, and a third electrically conductive film formed on said insulator film; and at least one electrode contact portion formed on said first electrically conductive film. A semiconductor device comprising a MIS capacitor having a diffusion layer inside the semiconductor substrate as a lower electrode with a first electrically conductive type being isolated using another diffusion layer having the opposite conductive type, and said another diffusion layer having the opposite conductive type being further isolated using a diffusion layer for isolation having the first conductive type and which is earthed. A BiCMOS semiconductor device comprising a resistor and an impurity source for the emitter and the emitter electrode for the bipolar transistor made of a same conductor layer, and further, a same conductor layer is provided as the contact electrode for the resistor and the gate for the MOS transistor. Also claimed are processes for fabricating the aforementioned semiconductor devices.
摘要翻译：一种包括MIS结构的半导体器件，包括形成在氧化膜上的第一导电膜，形成在所述第一导电膜的至少一部分上的第二导电膜，形成在所述第二导电膜上的绝缘膜，形成在所述绝缘膜上的第三导电膜; 以及形成在所述第一导电膜上的至少一个电极接触部分。一种半导体器件，包括具有扩散层的MIS电容器，该半导体衬底内的扩散层作为具有第一导电类型的下电极，使用具有相反导电类型的另一扩散层来隔离，并且所述另一个具有相反导电类型的扩散层进一步隔离使用具有第一导电类型并且接地的用于隔离的扩散层。一种BiCMOS半导体器件，包括电阻器和用于由相同导体层制成的双极晶体管的发射极和发射极的杂质源，并且还提供相同的导体层作为电阻器的接触电极和用于 MOS晶体管。还要求保护的是制造上述半导体器件的工艺。

9. 发明授权

US5163178A Semiconductor device having enhanced impurity concentration profile 失效
标题翻译：具有增强浓度浓度特性的半导体器件
公开(公告)号：US5163178A
公开(公告)日：1992-11-10
申请号：US634454
申请日：1990-12-27
申请人： Takayuki Gomi , Minoru Nakamura , Hiroaki Anmo , Norikazu Chuchi , Hiroyuki Miwa , Akio Kayanuma , Koji Kobayashi
发明人： Takayuki Gomi , Minoru Nakamura , Hiroaki Anmo , Norikazu Chuchi , Hiroyuki Miwa , Akio Kayanuma , Koji Kobayashi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8224 , H01L27/06 , H01L29/08 , H01L29/732 , H01L29/735
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8224 , H01L29/735
摘要： A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter region are formed within the semiconductor substrate. A method of fabricating a semiconductor device comprises a step of forming a collector region of a second conduction type and an emitter region of a second conduction type in a lateral arrangement in a semiconductor substrate serving as a base region of a first conduction type by using a first mask provided with a pair of openings, and a step of forming heavily doped regions of the second conduction type so as to be connected respectively to the collector region and the emitter region by using a second mask provided with a pair of openings separated from each other by a distance greater than the distance between the openings of the first mask.

10. 发明授权

US06977426B1 Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate 失效
标题翻译：半导体装置包括设置在单个基板上的高速晶体管和高压晶体管
公开(公告)号：US06977426B1
公开(公告)日：2005-12-20
申请号：US08965286
申请日：1997-11-06
申请人： Takayuki Gomi , Hiroaki Ammo
发明人： Takayuki Gomi , Hiroaki Ammo
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L29/732 , H01L29/00 , H01L27/082
CPC分类号： H01L21/8222
摘要： In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N+-type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.
摘要翻译：在包括形成在通过在硅衬底上形成外延层而制成的半导体衬底上的不同电压的第一双极晶体管和第二双极晶体管的半导体器件中，在硅衬底的上部中，第一双极晶体管具有N < 具有比外延层高的杂质浓度的第一嵌入扩散层和第二双极晶体管具有N型第二嵌入扩散层，其具有较低的杂质浓度和较深的扩散层深度第一嵌入式扩散层，由此在相同的衬底上形成高速双极晶体管和高电压双极晶体管。

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