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1. 发明申请

US20110156816A1 Biasing Circuit for Differential Amplifier 有权
标题翻译：差分放大器的偏置电路
公开(公告)号：US20110156816A1
公开(公告)日：2011-06-30
申请号：US12979135
申请日：2010-12-27
申请人： Eoin Ohannaidh
发明人： Eoin Ohannaidh
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , G05F3/245 , H03F1/26 , H03F1/3211 , H03F3/45197 , H03F3/45632 , H03F2200/447 , H03F2200/453 , H03F2200/456 , H03F2203/45244 , H03F2203/45286 , H03F2203/45468 , H03F2203/45484 , H03F2203/45508 , H03F2203/45702
摘要： The invention concerns a biasing circuit for controlling the current flowing through a differential pair (102, 104) comprising: a first branch comprising a first resistor (306), a first transistor device (308) and a second transistor device (310) coupled in series; a second branch comprising a second resistor (312), a third transistor device (314) and a fourth transistor device (316) coupled in series, a control node of the third transistor device being coupled to a first node (324) between the first resistor and the first transistor device, and a control node of the first transistor device being coupled to a second node (322) between the second resistor and the third transistor device; and an operational amplifier (318) having an output node coupled to control nodes of the second and fourth transistor devices, said output node providing a output signal (Vc) for controlling the current flowing through said differential pair.
摘要翻译：本发明涉及一种用于控制流过差分对（102,104）的电流的偏置电路，包括：第一分支，包括第一电阻器（306），第一晶体管器件（308）和第二晶体管器件（310）系列; 第二分支，包括串联耦合的第二电阻器（312），第三晶体管器件（314）和第四晶体管器件（316），所述第三晶体管器件的控制节点耦合到所述第一晶体管电阻器和第一晶体管器件，并且第一晶体管器件的控制节点耦合到第二电阻器和第三晶体管器件之间的第二节点（322）; 以及具有耦合到第二和第四晶体管器件的控制节点的输出节点的运算放大器（318），所述输出节点提供用于控制流过所述差分对的电流的输出信号（Vc）。

2. 发明申请

US20070024262A1 Integrated circuit apparatus and method of compensating a current 有权
标题翻译：集成电路装置及补偿电流的方法
公开(公告)号：US20070024262A1
公开(公告)日：2007-02-01
申请号：US11455376
申请日：2006-06-19
申请人： Fresseha Seifu , Marco Fornasari , Samir Aboulhouda
发明人： Fresseha Seifu , Marco Fornasari , Samir Aboulhouda
IPC分类号： G05F3/16
CPC分类号： H03F1/301 , H03F3/45085 , H03F3/45179 , H03F3/45484 , H03F2203/45286 , H03F2203/45482 , H03F2203/45484
摘要： An integrated circuit comprises a gain stage circuit couple to a compensation circuit. Both the gain stage circuit and the compensation circuit respectively comprise a first current source and a second current source that are subject to the same process variations. A negative feedback circuit is used to generate a corrective current in relation to the second current source, indicative of a current that needs to flow through a load in addition to a current flowing through the second current source in order for a variable voltage to be substantially equal to a reference voltage used to drive the first and second current sources. The corrective current generated for the second current source is applied to the first current source to compensate for process variation in the gain stage circuit in respect of the first current source.
摘要翻译：集成电路包括耦合到补偿电路的增益级电路。增益级电路和补偿电路都分别包括受到相同工艺变化的第一电流源和第二电流源。使用负反馈电路来产生相对于第二电流源的校正电流，其指示除了流过第二电流源的电流之外还需要流过负载的电流，以使可变电压基本上等于用于驱动第一和第二电流源的参考电压。为第二电流源产生的校正电流被施加到第一电流源，以补偿增益级电路中关于第一电流源的工艺变化。

3. 发明授权

US06850109B2 Linear voltage subtractor/adder circuit and MOS differential amplifier circuit therefor 失效
标题翻译：线性电压减法器/加法电路及其MOS差分放大电路
公开(公告)号：US06850109B2
公开(公告)日：2005-02-01
申请号：US09940472
申请日：2001-08-29
申请人： Katsuji Kimura
发明人： Katsuji Kimura
IPC分类号： G06G7/14 , H03F1/32 , H03F3/45 , H03G3/10 , G06F7/42
CPC分类号： H03F3/45717 , G06G7/14 , H03F3/45183 , H03F3/4565 , H03F3/4569 , H03F3/45708 , H03F3/45739 , H03F2203/45456 , H03F2203/45484 , H03F2203/45566 , H03F2203/45612 , H03F2203/45702
摘要： A voltage subtractor/adder circuit has a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.
摘要翻译：电压减法器/加法器电路具有具有第一和第二MOS晶体管的差分对。第一和第二MOS晶体管的栅电极形成用于接收输入差分电压的输入端。第一和第二MOS晶体管的漏极形成用于输出减法输出信号的输出端。第一和第二MOS晶体管的源电极共同耦合以形成用于加法输出电压的输出端。流过第一和第二MOS晶体管的电流的总和与输入差分电压的平方成比例地增加。也可以通过恒定电流源来驱动差分对。可以提供电平移位器用于对来自共同耦合的源电极的相加输出电压进行电平移位。

4. 发明授权

US08212616B2 Biasing circuit for differential amplifier 有权
标题翻译：差分放大器的偏置电路
公开(公告)号：US08212616B2
公开(公告)日：2012-07-03
申请号：US12979135
申请日：2010-12-27
申请人： Eoin Ohannaidh
发明人： Eoin Ohannaidh
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , G05F3/245 , H03F1/26 , H03F1/3211 , H03F3/45197 , H03F3/45632 , H03F2200/447 , H03F2200/453 , H03F2200/456 , H03F2203/45244 , H03F2203/45286 , H03F2203/45468 , H03F2203/45484 , H03F2203/45508 , H03F2203/45702
摘要： The invention concerns a biasing circuit for controlling the current flowing through a differential pair (102, 104) comprising: a first branch comprising a first resistor (306), a first transistor device (308) and a second transistor device (310) coupled in series; a second branch comprising a second resistor (312), a third transistor device (314) and a fourth transistor device (316) coupled in series, a control node of the third transistor device being coupled to a first node (324) between the first resistor and the first transistor device, and a control node of the first transistor device being coupled to a second node (322) between the second resistor and the third transistor device; and an operational amplifier (318) having an output node coupled to control nodes of the second and fourth transistor devices, said output node providing a output signal (Vc) for controlling the current flowing through said differential pair.
摘要翻译：本发明涉及一种用于控制流过差分对（102,104）的电流的偏置电路，包括：第一分支，包括第一电阻器（306），第一晶体管器件（308）和第二晶体管器件（310）系列; 第二分支，包括串联耦合的第二电阻器（312），第三晶体管器件（314）和第四晶体管器件（316），所述第三晶体管器件的控制节点耦合到所述第一晶体管电阻器和第一晶体管器件，并且第一晶体管器件的控制节点耦合到第二电阻器和第三晶体管器件之间的第二节点（322）; 以及具有耦合到第二和第四晶体管器件的控制节点的输出节点的运算放大器（318），所述输出节点提供用于控制流过所述差分对的电流的输出信号（Vc）。

5. 发明授权

US07948314B2 Tunable linear operational transconductance amplifier 有权
标题翻译：可调线性运算跨导放大器
公开(公告)号：US07948314B2
公开(公告)日：2011-05-24
申请号：US12473131
申请日：2009-05-27
申请人： Kunkun Zheng , Jianhua Zhao
发明人： Kunkun Zheng , Jianhua Zhao
IPC分类号： H03F3/45
CPC分类号： H03F3/45098 , H03F2203/45356 , H03F2203/45484 , H03F2203/45492 , H03F2203/45506 , H03F2203/45648 , H03F2203/45682
摘要： A tunable, linear operational transconductance amplifier includes a differential voltage to current conversion unit adapted to generate first and second output signals at respective first and second output nodes responsive to first and second differential input signals. A first current amplification unit is adapted to generate a third output signal responsive to the first output signal and first and second control signals. A second current amplification unit is adapted to generate a fourth output signal responsive to the second output signal and the first and second control signals.
摘要翻译：可调谐线性运算跨导放大器包括差分电压到电流转换单元，其适于响应于第一和第二差分输入信号在相应的第一和第二输出节点产生第一和第二输出信号。第一电流放大单元适于响应于第一输出信号和第一和第二控制信号产生第三输出信号。第二电流放大单元适于响应于第二输出信号和第一和第二控制信号产生第四输出信号。

6. 发明申请

US20020158686A1 Linear voltage subtractor/adder circuit and MOS differential amplifier circuit therefor 有权
公开(公告)号：US20020158686A1
公开(公告)日：2002-10-31
申请号：US10137298
申请日：2002-05-03
申请人： NEC CORPORATION
发明人： Katsuji Kimura
IPC分类号： G06G007/12
CPC分类号： H03F3/45717 , G06G7/14 , H03F3/45183 , H03F3/4565 , H03F3/4569 , H03F3/45708 , H03F3/45739 , H03F2203/45456 , H03F2203/45484 , H03F2203/45566 , H03F2203/45612 , H03F2203/45702
摘要： A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

7. 发明申请

US20090322428A1 TUNABLE LINEAR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER 有权
标题翻译：可调线性运算放大器
公开(公告)号：US20090322428A1
公开(公告)日：2009-12-31
申请号：US12473131
申请日：2009-05-27
申请人： Kunkun Zheng , Jianhua Zhao
发明人： Kunkun Zheng , Jianhua Zhao
IPC分类号： H03F3/45
CPC分类号： H03F3/45098 , H03F2203/45356 , H03F2203/45484 , H03F2203/45492 , H03F2203/45506 , H03F2203/45648 , H03F2203/45682
摘要： A tunable, linear operational transconductance amplifier includes a differential voltage to current conversion unit adapted to generate first and second output signals at respective first and second output nodes responsive to first and second differential input signals. A first current amplification unit is adapted to generate a third output signal responsive to the first output signal and first and second control signals. A second current amplification unit is adapted to generate a fourth output signal responsive to the second output signal and the first and second control signals.
摘要翻译：可调谐线性运算跨导放大器包括差分电压到电流转换单元，其适于响应于第一和第二差分输入信号在相应的第一和第二输出节点产生第一和第二输出信号。第一电流放大单元适于响应于第一输出信号和第一和第二控制信号产生第三输出信号。第二电流放大单元适于响应于第二输出信号和第一和第二控制信号产生第四输出信号。

8. 发明授权

US07427898B2 Detecting amplifier out-of-range conditions 有权
标题翻译：检测放大器超出范围的条件
公开(公告)号：US07427898B2
公开(公告)日：2008-09-23
申请号：US11462842
申请日：2006-08-07
申请人： Viola Schaffer , Mikhail Ivanov
发明人： Viola Schaffer , Mikhail Ivanov
IPC分类号： H03F3/04
CPC分类号： H03F3/303 , H03F3/45183 , H03F2203/45478 , H03F2203/45484
摘要： Out-of-range conditions are detected in amplifier CMOS or BiCMOS circuitry that includes a control transistor (MS) connected in series with a cascode transistor (MSC), and a differential amplifier (A1) with an inverting input connected to the node between the control transistor and the cascode transistor, a non-inverting input connected to a reference voltage source (VRDS) and an output connected to the gate of the cascode transistor (MSC). The voltage at the output of the differential amplifier (A1) is monitored, and an error condition is determined when the voltage exceeds or drops below a predetermined threshold value. The invention considerably widens the useful operating range, without requiring sophisticated or complex detection circuitry.
摘要翻译：在包括与共源共栅晶体管（M SUB SC）串联连接的控制晶体管（M SUB S S S）的放大器CMOS或BiCMOS电路中检测超范围条件，以及具有连接到控制晶体管和共源共栅晶体管之间的节点的反相输入的差分放大器（A 1），连接到参考电压源（VRDS DS）的非反相输入和连接的输出到共源共栅晶体管（M SUB SC）的栅极。监视差分放大器（A 1）输出端的电压，当电压超过或低于预定阈值时，确定出错状态。本发明显着地拓宽了有用的操作范围，而不需要复杂的或复杂的检测电路。

9. 发明授权

US07180358B2 CMOS exponential function generating circuit with temperature compensation technique 失效
标题翻译：具有温度补偿技术的CMOS指数函数发生电路
公开(公告)号：US07180358B2
公开(公告)日：2007-02-20
申请号：US11004432
申请日：2004-12-03
申请人： Jong Kee Kwon , Mun Yang Park , Jong Dae Kim , Won Chul Song
发明人： Jong Kee Kwon , Mun Yang Park , Jong Dae Kim , Won Chul Song
IPC分类号： G06G7/20
CPC分类号： H03F3/45928 , H03F3/45179 , H03F3/45475 , H03F2203/45212 , H03F2203/45482 , H03F2203/45484 , H03F2203/45508 , H03G7/001
摘要： Provided is a CMOS exponential function generating circuit capable of compensating for the exponential function characteristic according to temperature variations. The exponential function generating circuit includes an voltage scaler scaling the value of an external gain control voltage signal, an exponential function generating unit generating exponential function current and voltage in response to a signal output from the voltage scaler, a reference voltage generator providing a reference voltage to the exponential function generating unit, and a temperature compensator compensating for the exponential function characteristic according to temperature variations.
摘要翻译：提供了能够根据温度变化补偿指数函数特性的CMOS指数函数发生电路。指数函数发生电路包括缩放外部增益控制电压信号的值的电压缩放器，响应于从电压调节器输出的信号产生指数函数电流和电压的指数函数产生单元，提供参考电压的参考电压发生器到指数函数产生单元，以及根据温度变化补偿指数函数特性的温度补偿器。

10. 发明申请

US20020060598A1 Linear voltage subtractor/adder circuit and MOS differential amplifier circuit therefor 失效
标题翻译：线性电压减法器/加法电路及其MOS差分放大电路
公开(公告)号：US20020060598A1
公开(公告)日：2002-05-23
申请号：US09940472
申请日：2001-08-29
申请人： NEC CORPORATION
发明人： Katsuji Kimura
IPC分类号： G06G007/14
CPC分类号： H03F3/45717 , G06G7/14 , H03F3/45183 , H03F3/4565 , H03F3/4569 , H03F3/45708 , H03F3/45739 , H03F2203/45456 , H03F2203/45484 , H03F2203/45566 , H03F2203/45612 , H03F2203/45702
摘要： A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.
摘要翻译：电压减法器/加法器电路包括具有第一和第二MOS晶体管的差分对。第一和第二MOS晶体管的栅电极形成用于接收输入差分电压的输入端。第一和第二MOS晶体管的漏极形成用于输出减法输出信号的输出端。第一和第二MOS晶体管的源电极共同耦合以形成用于加法输出电压的输出端。流过第一和第二MOS晶体管的电流的总和与输入差分电压的平方成比例地增加。也可以通过恒定电流源来驱动差分对。可以提供电平移位器用于对来自共同耦合的源电极的相加输出电压进行电平移位。

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