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1. 发明公开

US20240072747A1 DIFFERENTIAL DRIVER HAVING INPUT SIGNAL-CONTROLLED COMMON-MODE REFERENCE 审中-公开
公开(公告)号：US20240072747A1
公开(公告)日：2024-02-29
申请号：US17894294
申请日：2022-08-24
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
发明人： Vamsikrishna Parupalli
IPC分类号： H03F3/45
CPC分类号： H03F3/4565 , H03F3/45183 , H03F3/45475
摘要： A differential amplifier provides improved signal swing and reduced common-mode output noise. The differential amplifier circuit includes a driver circuit with a first output for driving a first output of the differential amplifier and with a second output for driving a second output of the differential amplifier. The driver circuit has inputs for receiving a differential (complementary) pair of input signals at least one common-mode reference input for receiving a common-mode reference signal. The differential amplifier also includes a signal maxima detector having inputs for receiving the differential input signals that detects a maximum value between the individual signals, including any input common-mode voltage. The differential amplifier also includes a common-mode reference circuit that provides the common-mode reference signal and an input coupled to an output of the signal maxima detector, so that a common-mode voltage of the outputs is independent of power supply voltages provided to the driver circuit.

2. 发明公开

US20230253939A1 METHOD FOR PERFORMING COMMON MODE VOLTAGE RE-BIASING IN ANALOG FRONT-END CIRCUIT OF RECEIVER, ASSOCIATED COMMON MODE VOLTAGE RE-BIASING CIRCUIT, ASSOCIATED RECEIVER AND ASSOCIATED INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20230253939A1
公开(公告)日：2023-08-10
申请号：US17953348
申请日：2022-09-27
申请人： Realtek Semiconductor Corp.
发明人： Bing-Hung Chen
IPC分类号： H03F3/45 , G05F1/46
CPC分类号： H03F3/4565 , G05F1/461 , H03F2203/45072 , H03F2203/45421
摘要： A method for performing common mode voltage re-biasing in an analog front-end circuit of a receiver, an associated common mode voltage re-biasing circuit, the receiver and an associated integrated circuit are provided. The common mode voltage re-biasing circuit may include a control circuit and multiple switchable common mode voltage re-biasing sub-circuits. The control circuit generates at least one control signal according to a command, for controlling the common mode voltage re-biasing circuit to operate in a selected circuit configuration. The multiple switchable common mode voltage re-biasing sub-circuits select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration according to the at least one control signal to be the selected circuit configuration to perform common mode voltage re-biasing operations corresponding to the selected circuit configuration, respectively.

3. 发明申请

US20180152156A1 Operational Amplifier and Differential Amplifying Circuit Thereof 审中-公开
公开(公告)号：US20180152156A1
公开(公告)日：2018-05-31
申请号：US15818547
申请日：2017-11-20
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： KUAN-YU SHIH
IPC分类号： H03F3/45 , H03F1/02
CPC分类号： H03F3/45224 , H03F1/0211 , H03F3/45475 , H03F3/45636 , H03F3/4565 , H03F3/45654 , H03F2200/144 , H03F2200/267 , H03F2200/48 , H03F2203/45031 , H03F2203/45032 , H03F2203/45151 , H03F2203/45156 , H03F2203/45276 , H03F2203/45404 , H03F2203/45418 , H03F2203/45424 , H03F2203/45692
摘要： An operational amplifier and a differential amplifying circuit thereof. The differential amplifying circuit receives a differential input signal and outputs a differential output signal. The differential amplifying circuit includes an output port that has a first terminal and a second terminal, the differential output signal being outputted via the first and second terminals; a first transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; a second transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; and a third transistor pair receiving a control signal via two first ends and coupling to the first and second terminals respectively via two second ends. The control signal controls the third transistor pair to switch on or off and/or controls the current flowing therethrough.

4. 发明申请

US20180109227A1 AMPLIFIER WITH ADJUSTABLE GAIN 有权
公开(公告)号：US20180109227A1
公开(公告)日：2018-04-19
申请号：US15385871
申请日：2016-12-21
申请人： Faraday Technology Corp.
发明人： Chih-Huang Lin
IPC分类号： H03F1/30 , H03G3/30 , H03F3/45
CPC分类号： H03F1/301 , H03F3/211 , H03F3/45201 , H03F3/45237 , H03F3/45273 , H03F3/4565 , H03F2200/555 , H03F2203/45336 , H03F2203/45372 , H03F2203/45508 , H03F2203/45594 , H03G1/0029 , H03G1/0088 , H03G3/30
摘要： An amplifier with adjustable gain including a plurality of differential amplifiers and an output stage circuit is provided. Each of the differential amplifiers has at least one differential pair, two current terminals of each of the differential pairs are coupled by a connection structure, and the connection structure provides a negative feedback resistance. The differential amplifiers commonly receive a differential input signal pair, and output terminals of the differential amplifiers are coupled together. The output stage circuit inverts a voltage on the output terminals of the differential amplifiers to generate an output voltage. A direct current gain of the amplifier with adjustable gain is determined by adjusting at least one of working numbers of the differential amplifiers and the differential pairs.

5. 发明申请

US20170366147A1 DIFFERENTIAL CIRCUITS WITH CONSTANT GM BIAS 审中-公开
公开(公告)号：US20170366147A1
公开(公告)日：2017-12-21
申请号：US15633521
申请日：2017-06-26
申请人： INPHI CORPORATION
发明人： Rajasekhar NAGULAPALLI , Simon FOREY , Parmanand MISHRA
IPC分类号： H03F3/45 , H03F1/34
CPC分类号： H03F3/45183 , H03F1/34 , H03F3/45475 , H03F3/45479 , H03F3/4565 , H03F3/45659 , H03F2203/45008 , H03F2203/45022 , H03F2203/45112 , H03F2203/45244 , H03F2203/45642
摘要： The present invention is directed to electrical circuits and techniques thereof. More specifically, embodiments of the present invention provide a differential amplifier that has a differential amplifier section, a current source, and a feedback section. The differential amplifier section comprises NMOS transistors that receives two voltage inputs and generate a differential output. The current source provides a long tail for the differential amplifier section. The feedback section generates a feedback voltage based on a reference bias voltage. The feedback voltage is used by an amplifier to control the current source and to keep the biasing and gain of the differential amplifier substantially constant. There are other embodiments as well.

6. 发明授权

US09450540B2 Methods and apparatus for calibrating for transconductance or gain over process or condition variations in differential circuits 有权
标题翻译：用于校准差分电路中的跨导或增益过程或条件变化的方法和装置
公开(公告)号：US09450540B2
公开(公告)日：2016-09-20
申请号：US14595106
申请日：2015-01-12
申请人： QUALCOMM Incorporated
发明人： Miao Li , Li Sun , Zhi Zhu
IPC分类号： H03F3/45 , H03F1/30 , H03G3/30 , H03K19/003 , H03K19/0185
CPC分类号： H03F1/30 , H03F3/45076 , H03F3/45183 , H03F3/45197 , H03F3/4565 , H03F3/45766 , H03F2200/447 , H03F2200/543 , H03F2203/45048 , H03F2203/45101 , H03F2203/45116 , H03F2203/45244 , H03F2203/45456 , H03G1/0029 , H03G3/3036 , H03K19/00384 , H03K19/018528
摘要： An apparatus is provided. The apparatus includes a calibration circuit configured to generate a reference signal and at least one differential circuit each being configured to operate at a calibrated transconductance over process or condition variations based on the reference signal. The calibration circuit may be configured to generate the reference signal independent of the at least one differential circuit. A method for operating at least one differential circuit is provided. The method includes generating a reference signal and operating the at least one differential circuit at a calibrated transconductance or gain over process or condition variations based on the reference signal. The reference signal may be generated independently of the at least one differential circuit.
摘要翻译：提供了一种装置。该装置包括被配置为产生参考信号的校准电路和至少一个差分电路，每个差分电路被配置为基于参考信号在校准的跨导处超过过程或条件变化进行操作。校准电路可以被配置为独立于至少一个差分电路产生参考信号。提供了一种用于操作至少一个差分电路的方法。该方法包括产生参考信号并且以校准的跨导或基于参考信号的过程或条件变化的增益来操作至少一个差分电路。参考信号可以独立于至少一个差分电路产生。

7. 发明申请

US20150349734A1 DIFFERENTIAL AMPLIFIER WITH HIGH-SPEED COMMON MODE FEEDBACK 有权
标题翻译：具有高速共通模式反馈的差分放大器
公开(公告)号：US20150349734A1
公开(公告)日：2015-12-03
申请号：US14294308
申请日：2014-06-03
申请人： Texas Instruments Incorporated
发明人： Bumha Lee
IPC分类号： H03F3/45 , H03F1/02
CPC分类号： H03F3/45668 , H03F1/0233 , H03F3/45188 , H03F3/4565 , H03F3/45659 , H03F2200/129 , H03F2203/45008 , H03F2203/45082 , H03F2203/45084 , H03F2203/45116 , H03F2203/45404 , H03F2203/45418 , H03F2203/45424 , H03F2203/45508
摘要： The differential signals at the outputs of a differential amplifier quickly change in response to common mode changes in the output differential signals. The amplified input signals amplified by the differential amplifier quickly change in response to common mode changes in the differential signals input into the differential amplifier. A bias voltage input to the differential amplifier is isolated to remove low-frequency components from the bias voltage.
摘要翻译：差分放大器输出端的差分信号响应于输出差分信号中的共模变化而快速变化。由差分放大器放大的放大的输入信号响应于输入到差分放大器的差分信号的共模变化而快速变化。输入到差分放大器的偏置电压是隔离的，以从偏置电压中去除低频分量。

8. 发明申请

US20150200635A1 OPERATIONAL TRANSCONDUCTANCE AMPLIFIER, RECONFIGURABLE FULLY DIFFERENTIAL VOLTAGE SENSING AMPLIFIER AND RECONFIGURABLE FULLY DIFFERENTIAL CAPACITIVE SENSING AMPLIFIER 有权
标题翻译：操作电平放大器，可重新配置的全差分电压感应放大器和可重新配置的全差分电容式感应放大器
公开(公告)号：US20150200635A1
公开(公告)日：2015-07-16
申请号：US14321769
申请日：2014-07-01
申请人： National Taiwan University of Science and Technology
发明人： Tzu-Yun WANG , Min-Rui LAI , Sheng-Yu PENG
IPC分类号： H03F3/45
CPC分类号： H03F1/0272 , H03F1/223 , H03F3/45 , H03F3/45188 , H03F3/45228 , H03F3/45475 , H03F3/45479 , H03F3/4565 , H03F2203/45082 , H03F2203/45292 , H03F2203/45311 , H03F2203/45352 , H03F2203/45404 , H03F2203/45512 , H03F2203/45522 , H03F2203/45528 , H03F2203/45544 , H03F2203/45631
摘要： An operational transconductance amplifier includes a cascode differential-pair amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The cascode differential-pair amplifying circuit is configured for receiving a differential input voltage and for providing a differential output voltage. The bias driving circuit is configured for providing a first bias current to drive the cascode differential-pair amplifying circuit and for adjusting the transconductance of the transconductance amplifier. The bias driving circuit includes a first floating-gate transistor. The first floating-gate transistor is configured for adjusting the first bias current. The common mode feedback circuit is configured for adjusting a second bias current of the cascode differential-pair amplifying circuit according to the differential output voltage so that the differential output voltage is stabilized. A reconfigurable fully differential voltage sensing amplifier and a reconfigurable fully differential capacitive sensing amplifier are disclosed herein as well.
摘要翻译：运算跨导放大器包括共源共栅差分对放大电路，偏置驱动电路和共模反馈电路。共射共栅差分对放大电路被配置为接收差分输入电压并提供差分输出电压。偏置驱动电路被配置为提供第一偏置电流来驱动共源共栅差分对放大电路并用于调节跨导放大器的跨导。偏置驱动电路包括第一浮栅晶体管。第一浮栅晶体管被配置用于调整第一偏置电流。共模反馈电路被配置为根据差分输出电压调整共源共栅差分对放大电路的第二偏置电流，使差分输出电压稳定。本文还公开了可重新配置的全差分电压感测放大器和可重新配置的全差分电容式感测放大器。

9. 发明申请

US20140266830A1 TECHNIQUES TO REDUCE HARMONIC DISTORTIONS OF IMPEDANCE ATTENUATORS FOR LOW-POWER WIDEBAND HIGH-RESOLUTION DACS 有权
标题翻译：减少低功耗宽带高分辨率DAC的阻抗衰减器谐波失真的技术
公开(公告)号：US20140266830A1
公开(公告)日：2014-09-18
申请号：US13839763
申请日：2013-03-15
申请人： QUALCOMM INCORPORATED
发明人： Tongyu Song , Sang Min Lee , Derui Kong , Dongwon Seo
IPC分类号： H03M1/74
CPC分类号： H03M1/74 , H03F3/19 , H03F3/211 , H03F3/245 , H03F3/45192 , H03F3/4565 , H03F3/72 , H03F2203/45466 , H03F2203/45512 , H03F2203/45562 , H03F2203/45631 , H03F2203/45634 , H03F2203/45644 , H03F2203/45686 , H03F2203/45701 , H03F2203/45702 , H03F2203/7236 , H03M1/0614
摘要： A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.
摘要翻译：数模转换器（DAC）部分地包括响应于数字信号向一对当前求和节点提供电流的多个输入级，以及耦合在当前求和节点和输出端之间的阻抗衰减器的DAC。除了其他功能之外，阻抗衰减器还适用于增加输出负载的阻抗范围，以解决由于工艺，电压和温度的变化而导致的输出负载阻抗的变化，并且将由求和所看到的阻抗解耦节点从负载阻抗。阻抗衰减器还包括具有可编程共模增益带宽的差分输入差分输出放大器，以控制放大器的谐波失真。阻抗衰减器可选地包括一对交叉耦合电容器，以控制放大器的谐波失真。

10. 发明申请

US20120049960A1 PRE-DRIVER AND DIGITAL TRANSMITTER USING THE SAME 有权
标题翻译：使用它的预驱动和数字发射器
公开(公告)号：US20120049960A1
公开(公告)日：2012-03-01
申请号：US13221383
申请日：2011-08-30
申请人： Jer-Hao HSU
发明人： Jer-Hao HSU
IPC分类号： H03F3/45
CPC分类号： H03F3/45237 , H03F3/4565 , H03F2203/45082 , H03F2203/45418 , H04L25/0272 , H04L25/0282
摘要： A pre-driver includes first to fourth transistors and first and second impedance elements. The first transistor, coupled between the first output terminal and a first node, has a gate coupled to the first differential input terminal. The second transistor, coupled between the second differential output terminal and the first node, has a gate coupled to the second differential input terminal. The third transistor, coupled between the first differential output terminal and a second node, has a gate coupled to the first differential input terminal. The fourth transistor, coupled between the second differential output terminal and the second node, has a gate coupled to the second differential input terminal. The first and second impedance elements are coupled between the first differential output terminal and a third node, and coupled between the second differential output terminal and the third node, respectively, wherein the third node is biased to a preset voltage.
摘要翻译：预驱动器包括第一至第四晶体管和第一和第二阻抗元件。耦合在第一输出端和第一节点之间的第一晶体管具有耦合到第一差分输入端的栅极。耦合在第二差分输出端子和第一节点之间的第二晶体管具有耦合到第二差分输入端子的栅极。耦合在第一差分输出端子和第二节点之间的第三晶体管具有耦合到第一差分输入端子的栅极。耦合在第二差分输出端子和第二节点之间的第四晶体管具有耦合到第二差分输入端子的栅极。第一和第二阻抗元件耦合在第一差分输出端子和第三节点之间，并且分别耦合在第二差分输出端子和第三节点之间，其中第三节点被偏置到预置电压。

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