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1. 发明授权

US06848058B1 Power reduction circuit and method with multi clock branch control 有权
标题翻译：降压电路及多时钟分支控制方法
公开(公告)号：US06848058B1
公开(公告)日：2005-01-25
申请号：US09325882
申请日：1999-06-04
申请人： David E. Sinclair , Eric Young , Sami J. Haouili
发明人： David E. Sinclair , Eric Young , Sami J. Haouili
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3275 , G06F1/3287 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： A power consumption reduction circuit and method utilizes a memory clock source and a memory clock divider circuit that generates divided memory clock output signals as a plurality of corresponding independent clock signals to a number of different processing engines. A memory clock divider circuit and method selectively activates a plurality of independent clock signals in response to received condition data. In one embodiment, an engine clock source is also coupled through a switching circuit such that it is selectively output to one or more processing engines. The switching circuit disables the output from the engine clock based on register condition data. In another embodiment, a plurality of memory read latch circuits are controlled by a memory read latch control circuit. The memory read latch control circuit is operative to dynamically activate and deactivate the plurality of memory read latches based on detected memory read requests to facilitate memory access activity-based power reduction.
摘要翻译：功耗降低电路和方法利用存储器时钟源和存储器时钟分频器电路，其产生分配的存储器时钟输出信号作为多个对应的独立时钟信号到多个不同的处理引擎。存储器时钟分频器电路和方法响应于接收到的条件数据选择性地激活多个独立的时钟信号。在一个实施例中，发动机时钟源还通过开关电路耦合，使得其被选择性地输出到一个或多个处理引擎。开关电路基于寄存器条件数据禁止发动机时钟的输出。在另一实施例中，多个存储器读锁存器电路由存储器读锁存器控制电路控制。存储器读锁存器控制电路用于基于检测到的存储器读请求来动态激活和去激活多个存储器读锁存器，以便于基于存储器访问活动的功率降低。

2. 发明授权

US06657634B1 Dynamic graphics and/or video memory power reducing circuit and method 有权
标题翻译：动态图形和/或视频存储器功耗的降低电路及方法
公开(公告)号：US06657634B1
公开(公告)日：2003-12-02
申请号：US09257291
申请日：1999-02-25
申请人： David E. Sinclair , Eric Young
发明人： David E. Sinclair , Eric Young
IPC分类号： G06F13372
CPC分类号： G06F1/3218 , G06F1/3265 , G06F13/1668 , G09G5/363 , G09G2330/022 , Y02D10/153 , Y02D50/20
摘要： An apparatus and method dynamically controls the graphics and/or video memory power dynamically during idle periods of the memory interface during active system modes. In one embodiment, a memory request detector generates memory request indication data, such as data representing whether memory requests have been received within a predetermined time, based on detection of graphics and/or video memory requests during an active mode of the display system operation. A dynamic activity based memory power controller analyzes the memory request indication data and controls the power consumption of the graphics and/or video memory based on whether memory requests are detected.
摘要翻译：一种装置和方法在主动系统模式期间在存储器接口的空闲周期期间动态地控制图形和/或视频存储器功率。在一个实施例中，存储器请求检测器基于在显示系统操作的活动模式期间的图形和/或视频存储器请求的检测，产生存储器请求指示数据，诸如表示在预定时间内是否已经接收到存储器请求的数据。基于动态活动的存储器功率控制器分析存储器请求指示数据，并且基于是否检测到存储器请求来控制图形和/或视频存储器的功耗。

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