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1. 发明授权

US06515672B1 Managing prefetching from a data buffer 失效
标题翻译：从数据缓冲区管理预取
公开(公告)号：US06515672B1
公开(公告)日：2003-02-04
申请号：US09470971
申请日：1999-12-23
申请人： Gad S. Sheaffer , Roman Surgutchik , Oded Lempel
发明人： Gad S. Sheaffer , Roman Surgutchik , Oded Lempel
IPC分类号： G06F13372
CPC分类号： G09G3/3644 , G09G5/395 , G09G2360/12
摘要： A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer starting at a data buffer start address until the address of said last item.
摘要翻译：用于防止从缓冲器过度预取的方法和装置接收数据缓冲器中的最后数据集项目的地址，并且从数据缓冲器起始地址开始将数据从数据缓冲器读取到读数据流缓冲器中，直到所述最后一项。

2. 发明授权

US06646647B1 Display of images from tiled memory 有权
标题翻译：从平铺内存中显示图像
公开(公告)号：US06646647B1
公开(公告)日：2003-11-11
申请号：US09672453
申请日：2000-09-29
申请人： Roman Surgutchik , Gad S Shaeffer , Oded Lempel , Robert Valentine
发明人： Roman Surgutchik , Gad S Shaeffer , Oded Lempel , Robert Valentine
IPC分类号： G09G536
CPC分类号： G09G5/395 , G09G5/363 , G09G2360/121 , G09G2360/122
摘要： Embodiments of the present invention relate to displaying images from memory. A plurality of pixel attributes are retrieved from memory in a single memory transaction. At least one attribute corresponds to one scan line of a display and another attribute corresponds to another scan line of the display. A portion of one scan line using the corresponding pixel attribute is displayed. The pixel attributes corresponding to another scan line is stored in a buffer.
摘要翻译：本发明的实施例涉及从存储器显示图像。在单个存储器事务中从存储器检索多个像素属性。至少一个属性对应于显示器的一个扫描线，另一个属性对应于显示器的另一个扫描线。显示使用相应像素属性的一条扫描线的一部分。与另一扫描线对应的像素属性存储在缓冲器中。

3. 发明授权

US06647545B1 Method and apparatus for branch trace message scheme 有权
标题翻译：分支跟踪消息方案的方法和装置
公开(公告)号：US06647545B1
公开(公告)日：2003-11-11
申请号：US09503879
申请日：2000-02-14
申请人： Tsvika Kurts , Roman Surgutchik , Oded Lempel , Ittai Anati , Haim Lustig
发明人： Tsvika Kurts , Roman Surgutchik , Oded Lempel , Ittai Anati , Haim Lustig
IPC分类号： G06F944
CPC分类号： G06F11/348 , G06F11/3476 , G06F11/364
摘要： A processor includes a host interface unit capable of generating at least one branch trace message (BTM), the host interface unit is coupled to a memory so as to store the at least one BTM in the memory and the processor is embodied on an integrated circuit (IC).
摘要翻译：处理器包括能够生成至少一个分支跟踪消息（BTM）的主机接口单元，主机接口单元耦合到存储器，以便将至少一个BTM存储在存储器中，并且处理器体现在集成电路（我知道了）。

4. 发明申请

US20100138608A1 Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor 有权
标题翻译：用于处理器的微操作缓存中的管道包含和指令重新启动的方法和装置
公开(公告)号：US20100138608A1
公开(公告)日：2010-06-03
申请号：US12317959
申请日：2008-12-31
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ilhyun Kim , Ron Gabor , Lior Libis , Gregory Pribush
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/0864 , G06F12/0875 , G06F12/1045 , G06F12/126 , Y02D10/13
摘要： Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
摘要翻译：公开了用于指令重新启动并包含在处理器微操作高速缓存中的方法和装置。微操作高速缓存的实施例具有方式存储字段来记录存储相应宏指令的指令高速缓存方式。与存储指令的指令 - 高速缓存行相关联的指令缓存使用指示在微操作高速缓存命中时被更新。可以使用微操作高速缓存线中记录的指令高速缓存方式来定位使用中的指示。受害者缓存释放微操作在微操作高速缓存未命中同步之后的微操作队列中排队，响应于从指令缓存到受害缓存的驱逐。包含逻辑还定位并排除对应于所记录的指令 - 高速缓存方式的微操作高速缓存行，以响应于来自指令高速缓存的逐出。

5. 发明申请

US20050027974A1 Method and system for conserving resources in an instruction pipeline 审中-公开
标题翻译：在指令管道中节省资源的方法和系统
公开(公告)号：US20050027974A1
公开(公告)日：2005-02-03
申请号：US10630686
申请日：2003-07-31
申请人： Oded Lempel
发明人： Oded Lempel
IPC分类号： G06F9/00 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3867
摘要： Embodiments of the present invention provide a method, apparatus and system for conserving resources such as power resources in processor instruction pipelines. A branch prediction unit may predict whether a branch is to be taken and an instruction fetch unit may fetch a next sequential instruction. A control circuit may be coupled to the branch prediction unit. The control circuit may abort the next sequential instruction if the branch is predicted to be taken.
摘要翻译：本发明的实施例提供了一种用于节省诸如处理器指令管线中的功率资源的资源的方法，装置和系统。分支预测单元可以预测是否要采用分支，并且指令获取单元可以获取下一个顺序指令。控制电路可以耦合到分支预测单元。如果预测分支被采取，则控制电路可以中止下一个顺序指令。

6. 发明授权

US08782374B2 Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor 有权
标题翻译：在处理器的微操作高速缓存中包含TLB条目的方法和装置
公开(公告)号：US08782374B2
公开(公告)日：2014-07-15
申请号：US12326882
申请日：2008-12-02
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
IPC分类号： G06F12/00 , G06F13/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/0864 , G06F12/0875 , G06F12/1036 , G06F12/1045 , G06F12/126 , G06F2212/652 , Y02D10/13
摘要： Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.
摘要翻译：公开了在处理器微操作高速缓存中包含TLB（翻译后备缓冲器）的方法和装置。包含TLB条目的一些实施例具有响应于访问TLB条目设置的微操作高速缓存包含字段。包含逻辑可以刷新微操作高速缓存或微操作高速缓存的部分，并且每当其相关联的包含字段被设置时响应于TLB条目的替换或无效而清除相应的包含字段。前端处理器状态也可以被清除，并且在由TLB未命中引起替换时，指令被重新指定。

7. 发明申请

US20100138610A1 METHOD AND APPARATUS FOR INCLUSION OF TLB ENTRIES IN A MICRO-OP CACHE OF A PROCESSOR 有权
标题翻译：在处理器的微型高速缓存中包含TLB入口的方法和装置
公开(公告)号：US20100138610A1
公开(公告)日：2010-06-03
申请号：US12326882
申请日：2008-12-02
申请人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
发明人： Lihu Rappoport , Chen Koren , Franck Sala , Oded Lempel , Ido Ouziel , Ron Gabor , Gregory Pribush , Lior Libis
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0864 , G06F12/0875 , G06F12/1036 , G06F12/1045 , G06F12/126 , G06F2212/652 , Y02D10/13
摘要： Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.
摘要翻译：公开了在处理器微操作高速缓存中包含TLB（翻译后备缓冲器）的方法和装置。包含TLB条目的一些实施例具有响应于访问TLB条目设置的微操作高速缓存包含字段。包含逻辑可以刷新微操作高速缓存或微操作高速缓存的部分，并且每当其相关联的包含字段被设置时响应于TLB条目的替换或无效而清除相应的包含字段。前端处理器状态也可以被清除，并且在由TLB未命中引起替换时，指令被重新指定。

8. 发明授权

US06076144A Method and apparatus for identifying potential entry points into trace segments 失效
标题翻译：用于将潜在入口点识别为跟踪段的方法和装置
公开(公告)号：US06076144A
公开(公告)日：2000-06-13
申请号：US982083
申请日：1997-12-01
申请人： Guy Peled , Robert C. Valentine , Oded Lempel
发明人： Guy Peled , Robert C. Valentine , Oded Lempel
IPC分类号： G06F9/38 , G06F11/34 , G06F12/08
CPC分类号： G06F9/3804 , G06F12/0875 , G06F11/348
摘要： An apparatus includes a data array, control logic, an entry candidate table, and a future target table. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The entry candidate table is coupled to the control logic and is adapted to store offset information related to the position of a selected instruction within the trace segment. The future target table is coupled to the control logic and adapted to store a potential entry point into the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A control flow instruction is identified from the first plurality of instructions and the outcome of the control flow instruction is predicted. The control flow instruction has a predicted taken target address and a predicted not-taken target address corresponding to the outcome predicted. The predicted not-taken target address is stored.
摘要翻译：一种装置包括数据阵列，控制逻辑，条目候选表和未来目标表。控制逻辑耦合到数据阵列并且适于将指令的至少一个跟踪段存储到数据阵列中。入口候选表被耦合到控制逻辑，并且适于存储与跟踪段内的所选指令的位置相关的偏移信息。将来的目标表耦合到控制逻辑并且适于将潜在入口点存储到跟踪段中。用于缓存指令的方法包括将第一多个指令存储在第一跟踪段中。从第一多个指令中识别控制流程指令，并预测控制流程指令的结果。控制流程指令具有对应于预测结果的预测的目标地址和预测的未被采用的目标地址。存储预测的未采取的目标地址。

9. 发明授权

US09448879B2 Apparatus and method for implement a multi-level memory hierarchy 有权
标题翻译：用于实现多级存储器层次的装置和方法
公开(公告)号：US09448879B2
公开(公告)日：2016-09-20
申请号：US13994105
申请日：2011-12-22
申请人： Theodros Yigzaw , Oded Lempel , Hisham Shafi , Geeyarpuram N. Santhanakrishnan , Jose A. Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Mandelblat , Michael Mishaeli
发明人： Theodros Yigzaw , Oded Lempel , Hisham Shafi , Geeyarpuram N. Santhanakrishnan , Jose A. Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Mandelblat , Michael Mishaeli
IPC分类号： G06F11/00 , G06F11/10 , G06F11/14 , G06F11/07
CPC分类号： G06F11/1064 , G06F11/0793 , G06F11/1016 , G06F11/1407
摘要： An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.
摘要翻译：描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。例如，在一个实施例中，用于从指令获取错误中检测和恢复的指令处理装置包括：指令处理装置执行以下操作：响应于指令提取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问，其中如果所述指令不是来自投机访问，则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。

10. 发明申请

US20050262332A1 Method and system for branch target prediction using path information 审中-公开
标题翻译：使用路径信息进行分支目标预测的方法和系统
公开(公告)号：US20050262332A1
公开(公告)日：2005-11-24
申请号：US10404384
申请日：2003-03-31
申请人： Lihu Rappoport , Ronny Ronen , Nicolas Kacevas , Oded Lempel
发明人： Lihu Rappoport , Ronny Ronen , Nicolas Kacevas , Oded Lempel
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3848
摘要： A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.
摘要翻译：一种用于预测微处理器当前指令的分支目标的系统和方法，该系统包括存储间接分支指令和路径寄存器的高速缓存器。通过路径寄存器和分支指令上的异或运算，在某些分支上更新路径寄存器，然后向寄存器添加一个或多个位。通过对当前指令地址和路径寄存器的一部分执行操作来对高速缓存进行索引; 返回的条目（如果有的话）可以用于预测当前指令的目标。

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