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1. 发明授权

US09131242B2 System, method, and apparatus for scalable memory access 有权
标题翻译：用于可扩展内存访问的系统，方法和设备
公开(公告)号：US09131242B2
公开(公告)日：2015-09-08
申请号：US12367338
申请日：2009-02-06
申请人： Alexander G. MacInnis
发明人： Alexander G. MacInnis
IPC分类号： H04N7/12 , H04N19/433 , H04N19/53
CPC分类号： H04N19/433 , H04N19/53
摘要： Presented herein are system(s), method(s), and apparatus for scalable memory access. One example, among others, is a system for requesting services. The system includes one or more requesting node(s) for performing a function with real-time requirements, such as making requests. The one or more requesting node(s) indicates whether each of said requests is required or optional.
摘要翻译：这里呈现的是用于可扩展存储器访问的系统，方法和装置。其中一个例子是用于请求服务的系统。该系统包括用于执行具有实时要求的功能的一个或多个请求节点，诸如进行请求。一个或多个请求节点指示每个所述请求是否是必需的或是可选的。

2. 发明授权

US08989263B2 Inverse quantizer supporting multiple decoding processes 有权
公开(公告)号：US08989263B2
公开(公告)日：2015-03-24
申请号：US13079978
申请日：2011-04-05
申请人： Vivian Hsiun , Alexander G. MacInnis , Xiaodong Xie
发明人： Vivian Hsiun , Alexander G. MacInnis , Xiaodong Xie
IPC分类号： H04N7/18 , H04N19/93 , H04N19/105 , H04N19/176 , H04N19/129 , H04N19/61 , H04N19/60 , H04N19/12 , H04N19/124 , H04N19/127 , H04N19/126 , H04N19/136 , H04N19/186 , H04N19/157 , H04N19/162 , H04N19/44 , H04N19/82 , H04N19/42 , H04N19/423 , H04N5/46
CPC分类号： H04N19/93 , H04N5/46 , H04N19/105 , H04N19/12 , H04N19/124 , H04N19/126 , H04N19/127 , H04N19/129 , H04N19/136 , H04N19/157 , H04N19/162 , H04N19/176 , H04N19/186 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/82 , H04N21/8153
摘要： The present invention provides an apparatus for performing inverse quantization for multiple decoding standards, where the functional operations that comprise the inverse quantizer are modularly implemented and can be selectably performed. Each operation can be represented via a table entry in an associated memory area, with the functional operation being performed via reference to that table entry. Functional operations can be bypassed as needed if inverse quantization does not need to be performed on a set of data. Certain other processing operations can be performed between steps as needed to accommodate different coding standards. Macroblock data can be read from and written back to a common storage area, or a direct path is provided for writing the data directly to a subsequent inverse transform device.

3. 发明授权

US08913667B2 Video decoding system having a programmable variable-length decoder 有权
标题翻译：具有可编程可变长度解码器的视频解码系统
公开(公告)号：US08913667B2
公开(公告)日：2014-12-16
申请号：US10404387
申请日：2003-04-01
申请人： Vivian Hsiun , Alexander G. MacInnis , Xiaodong Xie
发明人： Vivian Hsiun , Alexander G. MacInnis , Xiaodong Xie
IPC分类号： H04N7/18 , H04N19/12 , H04N19/82 , G06F9/38 , H04N19/70 , H04N5/445 , G09G5/14 , H04N19/423 , H04N19/129 , H04N19/157 , H04N9/64 , H04N19/60 , H04N19/91 , G09G5/36 , H04N19/44 , H04N19/90 , H04N19/122 , H04N19/176 , H04N19/61 , G09G5/06 , G09G5/28 , G09G5/34 , G09G5/12
CPC分类号： H04N9/641 , G06F9/3861 , G06F9/3877 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G2310/0224 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/125 , H04N5/44504 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/15 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
摘要： Video decoding system having a programmable variable-length decoding accelerator. The system includes a decoder processor and a variable-length decoding accelerator. The variable-length decoding accelerator is coupled to the decoder processor and performs variable-length decoding operations on variable-length code in the video data stream. The variable-length decoding accelerator is capable of decoding variable-length code according to any of a plurality of decoding methods. In one embodiment, the variable-length decoder includes a plurality of code tables stored in memory and a code table selection register that is programmable to dictate which of the plurality of code tables is to be utilized to decode variable-length code. In one embodiment, the decoding system includes two variable-length decoding accelerators.
摘要翻译：具有可编程可变长度解码加速器的视频解码系统。该系统包括解码器处理器和可变长度解码加速器。可变长度解码加速器耦合到解码器处理器，并对视频数据流中的可变长度码执行可变长度解码操作。可变长度解码加速器能够根据多种解码方法中的任何一种解码可变长度码。在一个实施例中，可变长度解码器包括存储在存储器中的多个代码表以及可编程的代码表选择寄存器，用于指示多个代码表中的哪一个用于解码可变长度代码。在一个实施例中，解码系统包括两个可变长度解码加速器。

4. 发明授权

US08559797B2 System and method for personal video recording 有权
公开(公告)号：US08559797B2
公开(公告)日：2013-10-15
申请号：US11616681
申请日：2006-12-27
申请人： Alexander G. MacInnis
发明人： Alexander G. MacInnis
IPC分类号： H04N5/783 , H04N5/90
CPC分类号： H04N19/0003 , H04N5/76 , H04N5/783 , H04N9/87 , H04N19/107 , H04N21/4147 , H04N21/44 , H04N21/8455
摘要： A system and method for personal video recording (PVR) is provided for recording digitally encoded streams, and for playing back and decoding the recorded streams. The PVR system may receive the digitally encoded streams from a digital cable box or a network server. The system enables trick modes including fast forward and reverse mode displays at various speeds. The system an method for PVR may also be applied to digitally encoded streams without I-pictures, such as, for example, progressive refresh streams or HITS streams. Reverse decode and display may be implemented by starting at a suitable entry point, decoding quickly up to the point of the desired picture, and displaying the result, and repeating the process. Index tables of entry points may be used for proper operation in some modes where the entry points are entry pictures (E-pictures) which start a pattern of progressively refreshing I-slices.

5. 发明授权

US08493415B2 Graphics display system with video scaler 有权
标题翻译：具有视频缩放器的图形显示系统
公开(公告)号：US08493415B2
公开(公告)日：2013-07-23
申请号：US13079845
申请日：2011-04-05
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G5/00
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A method for processing video data includes performing by one or more processors and/or circuits in a video processing device, the one or more processors and/or circuits including a video scaler, a memory, and a scaler engine, functions including receiving a video image by the video processing device. The functions also include determining whether the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory or after reading the video image from the memory, and scaling the video image based on the determination. If the video scaler requires less memory bandwidth to scale the video image before writing the video image to the memory, performing by the one or more processors and/or circuits scaling of the video image in the video scaler using a video input clock of the video scaler to generate a first scaled video image.
摘要翻译：一种用于处理视频数据的方法包括由视频处理设备中的一个或多个处理器和/或电路执行包括视频缩放器，存储器和缩放器引擎的一个或多个处理器和/或电路，其功能包括接收视频图像由视频处理设备。这些功能还包括：在将视频图像写入存储器之前或者从存储器读取视频图像之后，确定视频缩放器是否需要更少的存储器带宽来缩放视频图像，以及基于该确定来缩放视频图像。如果在将视频图像写入存储器之前，视频缩放器需要更少的存储器带宽来缩放视频图像，则通过一个或多个处理器和/或电路使用视频的视频输入时钟对视频缩放器中的视频图像进行缩放缩放器以生成第一缩放视频图像。

6. 发明授权

US08194732B2 Integrated circuit with conversion capability for portable media player 有权
标题翻译：具有便携式媒体播放器转换功能的集成电路
公开(公告)号：US08194732B2
公开(公告)日：2012-06-05
申请号：US12180316
申请日：2008-07-25
申请人： Alexander G. MacInnis
发明人： Alexander G. MacInnis
IPC分类号： H04N11/02
CPC分类号： H04N21/4126 , H04N21/43615 , H04N21/4402 , H04N21/4621
摘要： Presented herein are system(s), method(s) and apparatus for an integrated circuit with conversion capabilities for transferring data to a portable media player. In one embodiment, there is presented an integrated circuit for providing video data. The integrated circuit comprises at least one input, at least one output, an encoder, and at least another output. At least one input receives video data. At least one output provides the video data to a display screen. The encoder encodes the video data into a particular compressed format. The at least another output for provides the video data in the particular compressed format to an interface.
摘要翻译：这里提出了具有用于将数据传送到便携式媒体播放器的转换能力的集成电路的系统，方法和装置。在一个实施例中，提出了一种用于提供视频数据的集成电路。集成电路包括至少一个输入，至少一个输出，编码器和至少另一个输出。至少一个输入接收视频数据。至少一个输出将视频数据提供给显示屏幕。编码器将视频数据编码成特定的压缩格式。所述至少另一个输出用于将特定压缩格式的视频数据提供给接口。

7. 发明授权

US08164601B2 Graphics display system with anti-flutter filtering and vertical scaling feature 有权
标题翻译：图形显示系统具有防颤滤波和垂直缩放功能
公开(公告)号：US08164601B2
公开(公告)日：2012-04-24
申请号：US12953168
申请日：2010-11-23
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G5/00 , G06K9/40 , H04N11/20 , H04N7/00
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形集成电路芯片。图形芯片处理模拟视频输入，数字视频输入和图形输入。该芯片包括单个多相滤波器，其优选地提供图像的防颤音滤波和缩放。防颤音滤波可能有助于减少由于电视显示器的隔行特性引起的显示闪烁。图形的缩放可以用于将图形的正方形像素长宽比转换为视频的正常矩形像素长宽比。

8. 发明申请

US20110314506A1 Point to multi-point wireless video delivery 审中-公开
标题翻译：指向多点无线视频传送
公开(公告)号：US20110314506A1
公开(公告)日：2011-12-22
申请号：US13220571
申请日：2011-08-29
申请人： Peyush Agarwal , Yasantha N. Rajakarunanayake , Alexander G. MacInnis , James D. Bennett , William S. Bunch , James F. Dougherty, III
发明人： Peyush Agarwal , Yasantha N. Rajakarunanayake , Alexander G. MacInnis , James D. Bennett , William S. Bunch , James F. Dougherty, III
IPC分类号： H04N7/16
CPC分类号： H04L1/1607 , H04L65/80 , H04L2001/0093 , H04N7/17318 , H04N21/43637 , H04N21/47202 , H04N21/6125 , H04N21/6375
摘要： Point to multi-point wireless video delivery. Among a group of receiver wireless communication devices (RXs), one is designated (e.g., as acknowledgment (ACK) leader). Media delivery operational parameters are selected based on the designated RX or based on all or a subset of the RXs. For simultaneous media delivery to multiple RXs, characteristics associated with the designated RX [or all, or a subset or RXs] govern the manner by which communications are made. Different respective RXs may be designated to serve in this role at different times. Wireless delivery of media (e.g., video signaling, audio signaling, etc.) to a group of RXs is effectuated in accordance with modified multicast signaling with a designated leader (e.g., ACK leader). Among a group of devices, a least successful receiving device that still receives media at an acceptable level may be chosen as the designated leader (e.g., ACK leader).
摘要翻译：指向多点无线视频传送。在一组接收机无线通信设备（RX）中，一个被指定（例如，作为确认（ACK）引导者）。基于指定的RX或基于RX的全部或一个子集来选择媒体传送操作参数。对于同时传送到多个RX的媒体，与指定的RX [或全部或子集或RXs]相关联的特征管理进行通信的方式。可以将不同的各个RX指定为在不同时间处于该角色。根据与指定的领导（例如，ACK领导者）的修改的多播信令，实现媒体（例如，视频信令，音频信令等）到一组RX的无线传送。在一组设备中，可以选择仍然以可接受的级别接收媒体的最不成功的接收设备作为指定的领导者（例如，ACK领导者）。

9. 发明授权

US08035751B2 Pulldown field detector 有权
标题翻译：下拉场检测器
公开(公告)号：US08035751B2
公开(公告)日：2011-10-11
申请号：US12567507
申请日：2009-09-25
申请人： Darren Neuman , Joseph Del Rio , Vadim Kochubievski , Craig Zinkievich , Shannon Posniewski , Alexander G. MacInnis
发明人： Darren Neuman , Joseph Del Rio , Vadim Kochubievski , Craig Zinkievich , Shannon Posniewski , Alexander G. MacInnis
IPC分类号： H04N9/64
CPC分类号： H04N7/0112
摘要： A system and method for detecting the presence and location of pull-down fields in a video field stream. Various aspects of the present invention may comprise method steps and circuit structure for generating an array of variance indications, each of which represents a degree of variance between two video fields in the video field stream. Various aspects may comprise comparing the array of variance indications to a pattern to detect a pull-down field in the video field stream. Various aspects may comprise comparing corresponding portions of video fields and generating a histogram of differences between the corresponding portions. Various aspects may comprise generating an indication of variance of the histogram and analyzing the indication of variance. Various aspects may comprise analyzing an array of such indications of variance and may comprise comparing the array of such indications to a pattern or plurality of patterns.
摘要翻译：一种用于检测视频场流中下拉字段的存在和位置的系统和方法。本发明的各个方面可以包括用于产生方差指示阵列的方法步骤和电路结构，每个方向指示表示视频字段流中的两个视频字段之间的方差。各个方面可以包括将方差指示阵列与模式进行比较以检测视频字段流中的下拉字段。各个方面可以包括比较视频场的对应部分并产生对应部分之间的差异直方图。各个方面可以包括生成直方图的方差的指示并分析方差的指示。各个方面可以包括分析这种方差指示的阵列，并且可以包括将这种指示的阵列与模式或多个模式进行比较。

10. 发明授权

US08005147B2 Method of operating a video decoding system 有权
标题翻译：操作视频解码系统的方法
公开(公告)号：US08005147B2
公开(公告)日：2011-08-23
申请号：US11400949
申请日：2006-04-05
申请人： Jose′ R. Alvarez , Alexander G. MacInnis , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
发明人： Jose′ R. Alvarez , Alexander G. MacInnis , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
IPC分类号： H04N7/18
CPC分类号： G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/13 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
摘要： A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.
摘要翻译：一种用于解码数字视频数据流的系统和方法。在一个方面，多个硬件加速模块与核心处理器一起使用。加速器在解码管线中操作，其中在任何给定阶段，每个加速器对视频数据的特定宏块进行操作。在随后的流水线阶段，每个加速器对数据流中的下一个宏块进行工作，该前一阶段的另一个加速器工作。核心处理器在每个阶段轮询所有加速器。当所有加速器在给定阶段完成任务时，核心处理器启动下一阶段。在另一方面，采用两个可变长度解码器来同时解码视频帧的两个宏块行。每个可变长度解码器用于对分配的行进行解码，并行并行地进行可变长度解码。可变长度解码器作为流水线的一部分进行操作，其中可变长度解码器逐级交替解码宏块。

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