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1. 发明授权

US08848792B2 Video and graphics system with video scaling 有权
标题翻译：视频和图形系统与视频缩放
公开(公告)号：US08848792B2
公开(公告)日：2014-09-30
申请号：US13195115
申请日：2011-08-01
申请人： Alexander MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Vivian Hsiun
发明人： Alexander MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Vivian Hsiun
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04 , H04N19/423 , H04N5/04 , H04N9/45 , H04N21/434 , H04N19/59 , G06T9/00 , H04N7/01 , H04N19/61 , H04N21/426 , G09G5/34 , G09G5/06 , H04N19/44 , G09G5/36 , G09G5/12 , H04N5/445 , H04N5/14 , H04N19/436 , H04N21/47 , G09G5/00 , H04N21/43 , H04N21/431 , H04N5/45 , H04N9/64 , G09G5/14 , H04N21/4402 , G09G5/28 , G06T1/20 , H04N21/422 , H04N19/42 , H04N21/443 , G09G5/02 , H04N5/44 , H04N5/46 , H04N5/12 , H04N11/20 , H04N11/14
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.
摘要翻译：视频和图形系统具有减小的存储模式，其中视频图像在解码期间在水平方向上减少一半。视频和图形系统包括用于解码MPEG-2视频数据的视频解码器。当不使用双向预测图像时，视频图像可能在水平方向上可能不被缩小。视频和图形系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。具有SDTV格式的输出可以在显示HDTV视频时使用录像机（VCR）进行记录。

2. 发明授权

US08390635B2 Graphics accelerator 有权
公开(公告)号：US08390635B2
公开(公告)日：2013-03-05
申请号：US12905617
申请日：2010-10-15
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F13/00
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

3. 发明申请

US20110280307A1 Video and Graphics System with Video Scaling 有权
标题翻译：视频和图形系统与视频缩放
公开(公告)号：US20110280307A1
公开(公告)日：2011-11-17
申请号：US13195115
申请日：2011-08-01
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Vivian Hsiun
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , Vivian Hsiun
IPC分类号： H04N7/32
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.
摘要翻译：视频和图形系统具有减小的存储模式，其中视频图像在解码期间在水平方向上减少一半。视频和图形系统包括用于解码MPEG-2视频数据的视频解码器。当不使用双向预测图像时，视频图像可能在水平方向上可能不被缩小。视频和图形系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。具有SDTV格式的输出可以在显示HDTV视频时使用录像机（VCR）进行记录。

4. 发明申请

US20110193868A1 GRAPHICS ACCELERATOR 有权
标题翻译：图形加速器
公开(公告)号：US20110193868A1
公开(公告)日：2011-08-11
申请号：US12905617
申请日：2010-10-15
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06T1/00 , G06F13/28
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.
摘要翻译：图形显示系统集成电路处理模拟视频输入，数字视频输入和图形输入。该系统包含一个图形加速器，包括用于图形数据的存储器。加速器优选地包括用于对图形数据的一个像素的多个分量执行向量类型操作的协处理器。加速器还包括用于存储和加载数据的扩展指令集。

5. 发明授权

US07961255B2 Television functionality on a chip 有权
标题翻译：芯片上的电视功能
公开(公告)号：US07961255B2
公开(公告)日：2011-06-14
申请号：US12367425
申请日：2009-02-06
申请人： David A. Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klinger , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
发明人： David A. Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klinger , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
IPC分类号： H04N5/44 , H04N3/27
CPC分类号： H04N21/426 , H04N5/4401 , H04N5/44504 , H04N5/46 , H04N7/035 , H04N21/4263 , H04N21/4305 , H04N2005/91364
摘要： A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.
摘要翻译：公开了一种提供用于在单个集成电路芯片上提供电视功能的成本有效方法的芯片上的电视（TVOC）系统。 TVOC包括以各种输入和输出格式接收和显示电视信号所必需的功能。 TVOC可用于有线和卫星电视的机顶盒，或直接在电视机内使用。所提供的所有功能可以在单个集成电路上提供。 TVOC包括数据传输模块，IF解调器，数字音频引擎，模拟音频引擎，数字视频引擎和模拟视频引擎。 TVOC还包括三套接口，包括输出接口，控制接口和辅助接口。其他特征和实施例提供增强的功能和提高的效率。

6. 发明申请

US20100110106A1 VIDEO AND GRAPHICS SYSTEM WITH PARALLEL PROCESSING OF GRAPHICS WINDOWS 审中-公开
标题翻译：视频和图形系统并行处理图形窗口
公开(公告)号：US20100110106A1
公开(公告)日：2010-05-06
申请号：US12642609
申请日：2009-12-18
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Greg A. Kranawetter
IPC分类号： G09G5/00
CPC分类号： G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2300/0408 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/0428 , G09G2340/06 , G09G2340/10 , G09G2340/12 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N9/45 , H04N9/641 , H04N9/642 , H04N9/75 , H04N9/78 , H04N11/143 , H04N11/20 , H04N19/112 , H04N19/16 , H04N19/186 , H04N19/20 , H04N19/27 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N19/80 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/4438 , H04N21/47
摘要： A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.
摘要翻译：视频和图形系统的显示引擎包括一个或多个处理元件并从存储器接收图形。图形数据定义多个图形层，并且处理元件并行处理两个或多个图形层以产生混合图形。混合图形时可以使用Alpha值。处理元件可以集成在具有用于接收图形数据和其他视频和图形部件的输入的集成电路芯片上。显示引擎还可以包括用于并行接收两个或更多图形层的图形控制器，用于以适于并行处理的顺序排列图形层，以及为处理元件提供布置的图形层。混合图形可以与HDTV视频或SDTV视频混合，HDTV视频或SDTV视频可以从诸如MPEG传输流的压缩数据流中提取。

7. 发明授权

US07667710B2 Graphics display system with line buffer control scheme 有权
标题翻译：具有行缓冲控制方案的图形显示系统
公开(公告)号：US07667710B2
公开(公告)日：2010-02-23
申请号：US11441782
申请日：2006-05-26
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G5/36 , G09G5/00
CPC分类号： G09G5/001 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/363 , G09G5/395 , G09G2310/0224 , G09G2320/0247 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/121 , G09G2360/125
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形集成电路芯片。图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。该芯片包括一个显示引擎，用于处理组织为Windows的图形图像。该系统包括用于接收图形内容的多个行缓冲器。将图形内容通过将图形内容与行缓冲存储器的现有内容进行混合直到所有行的所有图形表面都被合成，来合成到多个行缓冲器的每一行中。

8. 发明授权

US07595808B2 Method and apparatus for updating a color look-up table 有权
标题翻译：用于更新颜色查找表的方法和装置
公开(公告)号：US07595808B2
公开(公告)日：2009-09-29
申请号：US10955047
申请日：2004-09-30
申请人： Guang-Ting Shih , Jay Li , Steven Tseng , Chengfuh Jeffrey Tang
发明人： Guang-Ting Shih , Jay Li , Steven Tseng , Chengfuh Jeffrey Tang
IPC分类号： G09G5/02 , G09G5/36 , H04N5/44 , H04N9/69 , G06K9/00 , G03F3/08
CPC分类号： G09G5/06 , G09G1/162 , G09G5/001
摘要： Aspects of the invention may include a method updating a color look-up table (CLUT) for a next line of graphics before a current line of graphics has been completely read out of a graphics FIFO and assigned color pixel values. The method may include the step of formatting or arranging the CLUT into a plurality of sub-CLUTs. Each one of the sub-CLUTs may include pixel color values for each one of a plurality of pixels which may include a line of the graphics image data. Pixel color values may be read from within a first selected sub-CLUT, the first selected sub-CLUT comprising pixel color values for a first line of the graphics image data. The read pixel color value may be applied to the current first line of the graphics image data. While the read pixel color value is being applied to the current first line, pixel color values for a second selected sub-CLUT may be updated. The second selected sub-CLUT may include color pixel values for a second line of the graphics image data.
摘要翻译：本发明的各方面可以包括在图形的当前线已经完全从图形FIFO读出并分配的颜色像素值之前更新用于下一行图形的颜色查找表（CLUT）的方法。该方法可以包括将CLUT格式化或布置到多个子CLUT中的步骤。子CLUT中的每一个可以包括可以包括图形图像数据的一行的多个像素中的每一个的像素颜色值。可以从第一选择的子CLUT内读取像素颜色值，第一选择的子CLUT包括图形图像数据的第一行的像素颜色值。读取的像素颜色值可以应用于图形图像数据的当前第一行。当将读取像素颜色值应用于当前第一行时，可以更新第二选择子CLUT的像素颜色值。第二选择的子CLUT可以包括图形图像数据的第二行的颜色像素值。

9. 发明授权

US07554562B2 Graphics display system with anti-flutter filtering and vertical scaling feature 有权
标题翻译：图形显示系统具有防颤滤波和垂直缩放功能
公开(公告)号：US07554562B2
公开(公告)日：2009-06-30
申请号：US11959315
申请日：2007-12-18
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G09G5/00 , G09G5/397 , G06F3/38 , H04N7/01
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形集成电路芯片。图形芯片处理模拟视频输入，数字视频输入和图形输入。该芯片包括单个多相滤波器，其优选地提供图像的防颤音滤波和缩放。防颤音滤波可能有助于减少由于电视显示器的隔行特性引起的显示闪烁。图形的缩放可以用于将图形的正方形像素长宽比转换为视频的正常矩形像素长宽比。

10. 发明申请

US20090128572A1 VIDEO AND GRAPHICS SYSTEM WITH AN INTEGRATED SYSTEM BRIDGE CONTROLLER 有权
标题翻译：具有集成系统桥控制器的视频和图形系统
公开(公告)号：US20090128572A1
公开(公告)日：2009-05-21
申请号：US12235156
申请日：2008-09-22
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Greg A. Kranawetter
IPC分类号： G06F13/14
CPC分类号： G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2300/0408 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/0428 , G09G2340/06 , G09G2340/10 , G09G2340/12 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N9/45 , H04N9/641 , H04N9/642 , H04N9/75 , H04N9/78 , H04N11/143 , H04N11/20 , H04N19/112 , H04N19/16 , H04N19/186 , H04N19/20 , H04N19/27 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N19/80 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/4438 , H04N21/47
摘要： A video and graphics system on an integrated circuit chip includes an integrated system bridge controller to interface a CPU with devices internal to the system as well as external peripheral devices. The system bridge controller is capable of performing format conversion between big-endian data and little-endian data. The system bridge controller includes a PCI bridge to interface with PCI devices, an I/O bus bridge to interface with I/O devices such as RAM, ROM, flash memory and 68000-compatible peripheral devices, and a CPU interface block to interface the CPU to video processing devices on the integrated circuit chip such as an MPEG video decoder.
摘要翻译：集成电路芯片上的视频和图形系统包括集成系统桥接控制器，用于将CPU与系统内部的设备以及外部外围设备进行接口。系统桥控制器能够执行大端数据和小端数据之间的格式转换。系统桥控制器包括与PCI设备连接的PCI桥接器，与I / O设备（如RAM，ROM，闪存和68000兼容外围设备）进行接口的I / O总线桥接器，以及接口 CPU到视频处理设备上的集成电路芯片如MPEG视频解码器。

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