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1. 发明授权

US06781588B2 Texture engine memory access synchronizer 失效
公开(公告)号：US06781588B2
公开(公告)日：2004-08-24
申请号：US09964802
申请日：2001-09-28
申请人： Gavril Margittai , Zeev Sperber , Gabi Malka
发明人： Gavril Margittai , Zeev Sperber , Gabi Malka
IPC分类号： G06F1318
CPC分类号： G06T15/04
摘要： An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

2. 发明申请

US20090243734A1 METHOD AND DEVICE FOR DETERMINING A DUTY CYCLE OFFSET 失效
标题翻译：用于确定占空比偏移的方法和装置
公开(公告)号：US20090243734A1
公开(公告)日：2009-10-01
申请号：US12056783
申请日：2008-03-27
申请人： Gavril MARGITTAI
发明人： Gavril MARGITTAI
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K3/017
摘要： Embodiments of the present invention relate to a method and device operable to determine a duty cycle offset of a periodic signal and correct the periodic signal to a desired duty cycle. Embodiment of the present invention may include a ring oscillator circuit. The ring oscillator includes an odd number of ordered inverting elements. One or more of the inverting elements may be an inverting memory element. Each inverting element's output port (except the last inverting element) may be operably connected to the subsequent inverting element's input port. The last inverting element's output port may be operably connected to the first inverting element's input port, thereby forming a chain or ring. A counter may be incremented by oscillations of an output port of an inverting element during a high portion of a periodic signal and may be decremented by oscillations of the output port of the inverting element during a low portion of the periodic signal. The end result in the counter may be proportional to the duty cycle offset of the periodic signal. The end value may then be used to correct the duty cycle of the periodic signal to a desired duty cycle offset.
摘要翻译：本发明的实施例涉及一种可操作以确定周期性信号的占空比偏移并将周期信号校正到所需占空比的方法和装置。本发明的实施例可以包括环形振荡器电路。环形振荡器包括奇数个有序反转元件。反转元件中的一个或多个可以是反相存储元件。每个反相元件的输出端口（除了最后的反转元件之外）可以可操作地连接到后续的反相元件的输入端口。最后的反向元件的输出端口可以可操作地连接到第一反向元件的输入端口，从而形成链条或环。在周期信号的高部分期间，计数器可以由反相元件的输出端口的振荡增加，并且可以在周期信号的低部分期间由反相元件的输出端口的振荡而递减计数器。计数器的最终结果可能与周期信号的占空比偏移成比例。然后可以使用结束值来将周期信号的占空比校正到期望的占空比偏移。

3. 发明授权

US07612622B2 Method and device for determining a duty cycle offset 失效
标题翻译：用于确定占空比偏移的方法和装置
公开(公告)号：US07612622B2
公开(公告)日：2009-11-03
申请号：US12056783
申请日：2008-03-27
申请人： Gavril Margittai
发明人： Gavril Margittai
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K3/017
摘要： Embodiments of the present invention relate to a method and device operable to determine a duty cycle offset of a periodic signal and correct the periodic signal to a desired duty cycle. Embodiment of the present invention may include a ring oscillator circuit. The ring oscillator includes an odd number of ordered inverting elements. One or more of the inverting elements may be an inverting memory element. Each inverting element's output port (except the last inverting element) may be operably connected to the subsequent inverting element's input port. The last inverting element's output port may be operably connected to the first inverting element's input port, thereby forming a chain or ring. A counter may be incremented by oscillations of an output port of an inverting element during a high portion of a periodic signal and may be decremented by oscillations of the output port of the inverting element during a low portion of the periodic signal. The end result in the counter may be proportional to the duty cycle offset of the periodic signal. The end value may then be used to correct the duty cycle of the periodic signal to a desired duty cycle offset.
摘要翻译：本发明的实施例涉及一种可操作以确定周期性信号的占空比偏移并将周期信号校正到所需占空比的方法和装置。本发明的实施例可以包括环形振荡器电路。环形振荡器包括奇数个有序反转元件。反转元件中的一个或多个可以是反相存储元件。每个反相元件的输出端口（除了最后的反转元件之外）可以可操作地连接到后续的反相元件的输入端口。最后的反向元件的输出端口可以可操作地连接到第一反向元件的输入端口，从而形成链条或环。在周期信号的高部分期间，计数器可以由反相元件的输出端口的振荡增加，并且可以在周期信号的低部分期间由反相元件的输出端口的振荡而递减计数器。计数器的最终结果可能与周期信号的占空比偏移成比例。然后可以使用结束值来将周期信号的占空比校正到期望的占空比偏移。

4. 发明授权

US07202871B2 Texture engine memory access synchronizer 有权
标题翻译：纹理引擎内存访问同步器
公开(公告)号：US07202871B2
公开(公告)日：2007-04-10
申请号：US10843442
申请日：2004-05-12
申请人： Gavril Margittai , Zeev Sperber , Gabi Malka
发明人： Gavril Margittai , Zeev Sperber , Gabi Malka
IPC分类号： G06F13/18 , G06F15/80 , G06T1/20 , G06T11/40
CPC分类号： G06T15/04
摘要： An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.
摘要翻译：用于平衡多管道纹理引擎中的并行纹理管道发出的存储器请求的仲裁机制。该机制确保，由于纹理引擎处理多边形纹理，所有与给定图形纹理的一部分相关联的存储器请求将在任何纹理流水线发布对图形的另一部分的存储器请求之前由所有纹理管线发出质地。因此，本发明平衡了在一起操作的并行纹理管线之间的图形纹理处理，从而提高处理效率并防止死锁状况。

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