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1. 发明授权

US08487442B2 Semiconductor device having dual damascene structure 有权
标题翻译：具有双镶嵌结构的半导体器件
公开(公告)号：US08487442B2
公开(公告)日：2013-07-16
申请号：US13064394
申请日：2011-03-23
申请人： Toshiyuki Takewaki
发明人： Toshiyuki Takewaki
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/5283 , H01L21/76804 , H01L21/76808 , H01L23/5286 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, includes a semiconductor substrate, a first wiring layer formed on the semiconductor substrate, the first wiring layer containing a first via having a first aspect ratio and a first wire having a second aspect ratio, the first aspect ratio being equal to or larger than the second aspect ratio, and a second wiring layer overlying the first wiring layer, the second wiring layer containing a second via having a third aspect ratio and a second wire having a fourth aspect ratio, the third aspect ratio being smaller than the fourth aspect ratio.
摘要翻译：一种半导体器件，包括半导体衬底，形成在半导体衬底上的第一布线层，第一布线层包含具有第一纵横比的第一通孔和具有第二纵横比的第一布线，第一纵横比等于或等于大于第二纵横比的第二布线层和覆盖第一布线层的第二布线层，第二布线层包含具有第三纵横比的第二布线层和具有第四纵横比的第二布线，第三宽高比小于第四宽高比长宽比。

2. 发明授权

US08486836B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08486836B2
公开(公告)日：2013-07-16
申请号：US13228123
申请日：2011-09-08
申请人： Daisuke Oshida , Toshiyuki Takewaki , Takuji Onuma , Koichi Ohto
发明人： Daisuke Oshida , Toshiyuki Takewaki , Takuji Onuma , Koichi Ohto
IPC分类号： H01L21/02
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76883 , H01L21/76886 , H01L23/5223 , H01L23/5329 , H01L23/53295 , H01L28/60 , H01L2924/0002 , Y10S438/937 , H01L2924/00
摘要： A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.
摘要翻译：一种半导体器件，包括：衬底; 形成在基板上的绝缘膜; 铜互连，其表面上形成有多个隐藏在绝缘膜中的小丘; 形成在所述绝缘膜和所述铜互连上的第一绝缘夹层; 形成在所述第一绝缘夹层上的第二绝缘夹层; 以及形成在所述第二绝缘中间层上的导电层，其中提供了所有小丘中至少一个小丘的最高顶部表面与所述第二绝缘中间层的下表面接触。

3. 发明申请

US20120115324A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A REFRACTORY METAL CONTAINING FILM 审中-公开
标题翻译：制造含有金属薄膜的半导体器件的方法
公开(公告)号：US20120115324A1
公开(公告)日：2012-05-10
申请号：US13014282
申请日：2011-01-26
申请人： Toshiyuki TAKEWAKI , Mari WATANABE
发明人： Toshiyuki TAKEWAKI , Mari WATANABE
IPC分类号： H01L21/768
CPC分类号： H01L23/5256 , H01L24/03 , H01L24/11 , H01L2224/0401 , H01L2224/05559 , H01L2224/05567 , H01L2224/1147 , H01L2224/1148 , H01L2224/11902 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2film provided on the silicon substrate, copper films embedded in the SiO2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO2 film, and SiON films covering an upper face of the TiN films.
摘要翻译：本发明的半导体器件及其制造方法，其中半导体器件具有熔丝结构或电极焊盘结构，可以抑制铜含铜金属膜的吹出。半导体器件包括硅衬底，设置在硅衬底上的SiO 2膜，嵌入SiO 2膜中的铜膜，覆盖铜膜上表面与铜膜之间的边界区域的上表面的TiN膜和SiO 2膜，和覆盖TiN膜的上表面的SiON膜。

4. 发明申请

US20120108060A1 SEMICONDUCTOR DEVICE HAVING SILICON-DIFFUSED METAL WIRING LAYER AND ITS MANUFACTURING METHOD 有权
标题翻译：具有硅分散金属接线层的半导体器件及其制造方法
公开(公告)号：US20120108060A1
公开(公告)日：2012-05-03
申请号：US13348364
申请日：2012-01-11
申请人： Koichi OHTO , Toshiyuki TAKEWAKI , Tatsuya USAMI , Nobuyuki YAMANISHI
发明人： Koichi OHTO , Toshiyuki TAKEWAKI , Tatsuya USAMI , Nobuyuki YAMANISHI
IPC分类号： H01L21/28
CPC分类号： H01L21/022 , H01L21/02074 , H01L21/02118 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/3124 , H01L21/3148 , H01L21/31633 , H01L21/318 , H01L21/3185 , H01L21/32136 , H01L21/76801 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76814 , H01L21/76834 , H01L21/76838 , H01L21/76849 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L21/76889 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
摘要翻译：在半导体器件中，在绝缘底层上形成具有凹槽的绝缘中间层。不含金属硅化物的硅扩散金属层埋入槽内。在硅扩散金属层和绝缘中间层上形成金属扩散阻挡层。

5. 发明授权

US08030737B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08030737B2
公开(公告)日：2011-10-04
申请号：US11971925
申请日：2008-01-10
申请人： Daisuke Oshida , Toshiyuki Takewaki , Takuji Onuma , Koichi Ohto
发明人： Daisuke Oshida , Toshiyuki Takewaki , Takuji Onuma , Koichi Ohto
IPC分类号： H01L21/02 , H01L29/92
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76883 , H01L21/76886 , H01L23/5223 , H01L23/5329 , H01L23/53295 , H01L28/60 , H01L2924/0002 , Y10S438/937 , H01L2924/00
摘要： A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.
摘要翻译：一种半导体器件，包括：衬底; 形成在基板上的绝缘膜; 铜互连，其表面上形成有多个隐藏在绝缘膜中的小丘; 形成在所述绝缘膜和所述铜互连上的第一绝缘夹层; 形成在所述第一绝缘夹层上的第二绝缘夹层; 以及形成在所述第二绝缘中间层上的导电层，其中提供了所有小丘中至少一个小丘的最高顶部表面与所述第二绝缘中间层的下表面接触。

6. 发明授权

US07955980B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07955980B2
公开(公告)日：2011-06-07
申请号：US12543128
申请日：2009-08-18
申请人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
发明人： Toshiyuki Takewaki , Manabu Iguchi , Daisuke Oshida , Hironori Toyoshima , Masayuki Hiroi , Takuji Onuma , Hiroaki Nanba , Ichiro Honma , Mieko Hasegawa , Yasuaki Tsuchiya , Toshiji Taiji , Takaharu Kunugi
IPC分类号： H01L21/44
CPC分类号： H01L21/02074 , H01L21/76883
摘要： A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.
摘要翻译：如下进行铜层的CMP后清洗工序。依次使碱性水溶液，多元羧酸，BTA和碱性水溶液与设置有铜层的硅基板的主面接触。

7. 发明授权

US07687917B2 Single damascene structure semiconductor device having silicon-diffused metal wiring layer 有权
标题翻译：具有硅扩散金属布线层的单镶嵌结构半导体器件
公开(公告)号：US07687917B2
公开(公告)日：2010-03-30
申请号：US10650193
申请日：2003-08-28
申请人： Koichi Ohto , Toshiyuki Takewaki , Tatsuya Usami , Nobuyuki Yamanishi
发明人： Koichi Ohto , Toshiyuki Takewaki , Tatsuya Usami , Nobuyuki Yamanishi
IPC分类号： H01L23/48
CPC分类号： H01L21/022 , H01L21/02074 , H01L21/02118 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/02203 , H01L21/02211 , H01L21/02274 , H01L21/3124 , H01L21/3148 , H01L21/31633 , H01L21/318 , H01L21/3185 , H01L21/32136 , H01L21/76801 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/76808 , H01L21/7681 , H01L21/76814 , H01L21/76834 , H01L21/76838 , H01L21/76849 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L21/76889 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
摘要翻译：在半导体器件中，在绝缘底层上形成具有凹槽的绝缘中间层。不含金属硅化物的硅扩散金属层埋入槽内。在硅扩散金属层和绝缘中间层上形成金属扩散阻挡层。

8. 发明授权

US07674704B2 Method of manufacturing a semiconductor device having an interconnect structure that increases in impurity concentration as width increases 有权
标题翻译：具有随着宽度增加而杂质浓度增加的互连结构的半导体器件的制造方法
公开(公告)号：US07674704B2
公开(公告)日：2010-03-09
申请号：US12366870
申请日：2009-02-06
申请人： Toshiyuki Takewaki
发明人： Toshiyuki Takewaki
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76877 , H01L23/5283 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of interconnect layers, and an interconnect in at least one interconnect layer among the plurality of interconnect layers contains an impurity, and the wider the interconnect in the at least one interconnect layer is, the higher concentration of the impurity the interconnect contains.
摘要翻译：本发明提供能够抑制窄互连的电阻的增加同时保持宽互连的可靠性降低的半导体器件。半导体器件包括多个互连层，并且多个互连层中的至少一个互连层中的互连包含杂质，并且所述至少一个互连层中的互连越宽，杂质浓度越高互连包含。

9. 发明申请

US20090121360A1 Semiconductor device having dual damascene structure 有权
标题翻译：具有双镶嵌结构的半导体器件
公开(公告)号：US20090121360A1
公开(公告)日：2009-05-14
申请号：US12289905
申请日：2008-11-06
申请人： Toshiyuki Takewaki
发明人： Toshiyuki Takewaki
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/5283 , H01L21/76804 , H01L21/76808 , H01L23/5286 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes multilayer wirings of a dual damascene structure. The multilayer wirings include a first wiring layer formed on a semiconductor substrate and a second wiring layer formed on the first wiring layer. The first wiring layer includes a first insulation film, plural first vias provided in the first insulation film, a second insulation film provided on the first insulation film, and a first wiring provided on the first vias and connected to those first vias in the second insulation film. The second wiring layer includes a third insulation film, plural second vias provided in the third insulation film, an adhesive layer provided on the third insulation film, a fourth insulation film provided on the adhesive layer, and a second wiring provided on the second vias and connected to those second vias in the fourth insulation film. In the first wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V are in a relationship of L≧V and in the second wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V is in a relationship of L
摘要翻译：半导体器件包括双镶嵌结构的多层布线。多层布线包括形成在半导体衬底上的第一布线层和形成在第一布线层上的第二布线层。第一布线层包括第一绝缘膜，设置在第一绝缘膜中的多个第一通孔，设置在第一绝缘膜上的第二绝缘膜，以及设置在第一通孔上并连接到第二绝缘体中的第一通孔的第一布线电影。第二布线层包括第三绝缘膜，设置在第三绝缘膜中的多个第二通孔，设置在第三绝缘膜上的粘合层，设置在粘合剂层上的第四绝缘膜，以及设置在第二通孔上的第二布线，连接到第四绝缘膜中的那些第二通孔。在第一布线层中，具有最小布线宽度和通孔宽高比V的布线的纵横比L处于L> = V的关系，并且在第二布线层中，具有最小布线宽度的布线的纵横比L 布线宽度和通孔宽高比V处于L

10. 发明申请

US20090081870A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING COPPER WIRING LAYERS OF DIFFERENT WIDTHS HAVING METAL CAPPING LAYERS OF DIFFERENT THICKNESSES FORMED THEREON 失效
标题翻译：形成具有形成其不同厚度的金属覆盖层的不同宽度的铜覆铜层的半导体器件的方法
公开(公告)号：US20090081870A1
公开(公告)日：2009-03-26
申请号：US12325670
申请日：2008-12-01
申请人： Toshiyuki Takewaki , Kazuyoshi Ueno
发明人： Toshiyuki Takewaki , Kazuyoshi Ueno
IPC分类号： H01L21/44
CPC分类号： H01L23/53238 , H01L21/2885 , H01L21/76843 , H01L21/76849 , H01L21/76877 , H01L2924/0002 , Y10S438/978 , H01L2924/00
摘要： In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.
摘要翻译：在半导体装置中，在半导体基板的上方设置绝缘中间层，在绝缘中间层中形成有多个第一布线层和多个第二布线层。第一布线层基本上由铜组成，并以大间距平行布置。第二布线层基本上由铜组成，并以小的间距平行布置。第一金属覆盖层形成在每个第一布线层上，第二金属覆盖层形成在每个第二布线层上。第二金属覆盖层的厚度小于第一金属覆盖层的厚度。

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