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1. 发明授权

US07163894B2 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same 失效
公开(公告)号：US07163894B2
公开(公告)日：2007-01-16
申请号：US10927079
申请日：2004-08-27
申请人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
发明人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/32134 , H01L21/7682 , H01L21/76843 , H01L21/76862 , H01L21/76865 , H01L21/76897 , H01L23/5222 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

2. 发明授权

US07235882B2 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same 失效
标题翻译：具有镶嵌结构的布线层的半导体器件及其制造方法
公开(公告)号：US07235882B2
公开(公告)日：2007-06-26
申请号：US11121976
申请日：2005-05-05
申请人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
发明人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
IPC分类号： H01L23/52 , H01L23/34
CPC分类号： H01L21/76846 , H01L21/32134 , H01L21/7682 , H01L21/76843 , H01L21/76862 , H01L21/76865 , H01L21/76897 , H01L23/5222 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.
摘要翻译：在半导体器件中，在设置在半导体衬底上的氧化硅膜的表面部分中形成布线图案槽。布线层被埋入布线图案槽中，其间插入阻挡金属膜。从布线图形槽的各侧壁部选择性地去除阻挡金属膜。换句话说，阻挡金属膜仅留在布线图案槽的底部。因此，可以在半导体器件中形成具有在布线图案槽的每个侧壁和布线层的每一侧之间的介电常数低的中空部的镶嵌布线层。

3. 发明申请

US20050023696A1 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same 失效
公开(公告)号：US20050023696A1
公开(公告)日：2005-02-03
申请号：US10927079
申请日：2004-08-27
申请人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
发明人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
IPC分类号： H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/532 , H01L27/108 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/32134 , H01L21/7682 , H01L21/76843 , H01L21/76862 , H01L21/76865 , H01L21/76897 , H01L23/5222 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

4. 发明申请

US20050206002A1 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same 失效
标题翻译：具有镶嵌结构的布线层的半导体器件及其制造方法
公开(公告)号：US20050206002A1
公开(公告)日：2005-09-22
申请号：US11121976
申请日：2005-05-05
申请人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
发明人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
IPC分类号： H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/532 , H01L27/108 , H01L21/4763 , H01L23/48
CPC分类号： H01L21/76846 , H01L21/32134 , H01L21/7682 , H01L21/76843 , H01L21/76862 , H01L21/76865 , H01L21/76897 , H01L23/5222 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.
摘要翻译：在半导体器件中，在设置在半导体衬底上的氧化硅膜的表面部分中形成布线图案槽。布线层被埋入布线图案槽中，其间插入阻挡金属膜。从布线图形槽的各侧壁部选择性地去除阻挡金属膜。换句话说，阻挡金属膜仅留在布线图案槽的底部。因此，可以在半导体器件中形成具有在布线图案槽的每个侧壁和布线层的每一侧之间的介电常数低的中空部的镶嵌布线层。

5. 发明授权

US06906419B2 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same 失效
公开(公告)号：US06906419B2
公开(公告)日：2005-06-14
申请号：US09883210
申请日：2001-06-19
申请人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
发明人： Hiroyuki Nitta , Yoshiaki Fukuzumi , Yusuke Kohyama
IPC分类号： H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/532 , H01L27/108 , H01L29/76 , H01L29/00
CPC分类号： H01L21/76846 , H01L21/32134 , H01L21/7682 , H01L21/76843 , H01L21/76862 , H01L21/76865 , H01L21/76897 , H01L23/5222 , H01L23/5329 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

6. 发明授权

US06225230B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06225230B1
公开(公告)日：2001-05-01
申请号：US08861736
申请日：1997-05-22
申请人： Hiroyuki Nitta , Yusuke Kohyama
发明人： Hiroyuki Nitta , Yusuke Kohyama
IPC分类号： H01L2100
CPC分类号： H01L21/76229
摘要： Disclosed is a method of forming an element isolation insulating film by STI (shallow trench isolation) method, which permits effectively preventing a concave portion from being formed in an edge of the element isolation insulating film, permits decreasing the number of treating steps, and also permits facilitating the formation of the element isolation insulating film with a high yield. In forming the element isolation insulating film, a groove is formed in a surface region of a semiconductor substrate, followed by forming an insulating film on the entire surface to fill at least the groove. Then, a flattening treatment is applied at least once to remove the insulating film from the substrate surface such that the insulating film is left unremoved only within the groove. In place of a wet etching treatment, a mirror-polishing method is employed for the last flattening treatment.
摘要翻译：公开了通过STI（浅沟槽隔离）方法形成元件隔离绝缘膜的方法，其可有效地防止在元件隔离绝缘膜的边缘中形成凹部，从而减少处理步骤的数量，并且还允许以高产率促进元件隔离绝缘膜的形成。在形成元件隔离绝缘膜时，在半导体衬底的表面区域中形成沟槽，然后在整个表面上形成绝缘膜以至少填充沟槽。然后，平坦化处理至少施加一次以从基板表面去除绝缘膜，使得绝缘膜仅在沟槽内不被移除。代替湿蚀刻处理，最后的平坦化处理采用镜面抛光方法。

7. 发明授权

US08154560B2 Display drive circuit 有权
标题翻译：显示驱动电路
公开(公告)号：US08154560B2
公开(公告)日：2012-04-10
申请号：US12468345
申请日：2009-05-19
申请人： Yoshiki Kurokawa , Yasuyuki Kudo , Hiroyuki Nitta , Kazuki Homma , Junya Takeda
发明人： Yoshiki Kurokawa , Yasuyuki Kudo , Hiroyuki Nitta , Kazuki Homma , Junya Takeda
IPC分类号： G09G5/00 , G09G5/02 , H04N1/46 , H04N1/60 , G06T1/00 , G06K9/00 , G06K9/40
CPC分类号： G09G1/002 , G09G3/3655 , G09G5/04 , G09G5/06 , G09G2320/0242 , G09G2340/145
摘要： A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.
摘要翻译：本发明的显示驱动电路具有：能够存储初始色域顶点坐标的初始色域 - 顶点坐标存储单元; 能够存储用户目标色域顶点坐标的用户对象色彩 - 顶点坐标存储单元; 饱和扩张系数决定单元，用于基于初始和用户目标色域顶点坐标来确定饱和度数据的扩展系数; 以及用于基于饱和度膨胀系数扩大显示数据的饱和度的扩展单元。基于初始和用户目标色域顶点坐标来确定饱和度数据的扩展系数，根据扩展系数扩展显示数据的饱和度。因此，可以对于每个色域或LC显示面板的R，G和B颜色属性中的每一个来控制饱和度的扩大程度。

8. 发明授权

US08008704B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08008704B2
公开(公告)日：2011-08-30
申请号：US12372505
申请日：2009-02-17
申请人： Hiroyuki Nitta
发明人： Hiroyuki Nitta
IPC分类号： H01L21/00
CPC分类号： H01L27/11524 , H01L21/764 , H01L23/5222 , H01L27/11521 , H01L2924/0002 , H01L2924/00
摘要： To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. A void part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto. A bottom and two sides of each void part are shielded by the second insulating film, and a top of each void part is shielded by the third insulating film.
摘要翻译：为了减小半导体存储器件中每个相邻两个字线之间的电容，在每个相邻的两个存储晶体管的栅极之间的间隙中形成第一绝缘膜，其间具有第一栅极绝缘膜，并且在栅极的选择晶体管和与其相邻的存储晶体管的栅极。此外，第二绝缘膜形成在第一绝缘膜上，每个存储晶体管的栅极的侧面和面向存储晶体管的选择性晶体管的栅极的一侧。第三绝缘膜平行于半导体衬底形成以覆盖金属硅化物膜，第一和第二绝缘膜以及第四和第五绝缘膜。在存储晶体管的每个相邻的两个栅极之间的间隙中以及与选择晶体管的栅极和与其相邻的存储晶体管的栅极之间的空隙中设置空隙部分。每个空隙部分的底部和两侧被第二绝缘膜屏蔽，并且每个空隙部分的顶部被第三绝缘膜屏蔽。

9. 再颁专利

USRE42597E1 Liquid crystal driver and liquid crystal display device using the same 有权
标题翻译：液晶驱动器和液晶显示装置使用相同
公开(公告)号：USRE42597E1
公开(公告)日：2011-08-09
申请号：US11980691
申请日：2007-10-31
申请人： Hiroyuki Nitta , Hiroyuki Mano , Tsutomu Furuhashi , Isao Takita , Satoru Tsunekawa , Toshio Futami , Makiko Ikeda
发明人： Hiroyuki Nitta , Hiroyuki Mano , Tsutomu Furuhashi , Isao Takita , Satoru Tsunekawa , Toshio Futami , Makiko Ikeda
IPC分类号： G09G3/36
CPC分类号： G09G3/2011 , G09G3/3614 , G09G3/3655 , G09G3/3688 , G09G3/3696 , G09G2310/0248 , G09G2310/027 , G09G2310/0281 , G09G2310/0289 , G09G2310/0297 , G09G2330/023
摘要： A liquid crystal driver includes a voltage generator for generating gray scale voltages on the basis of reference voltages, and an output device for selecting one gray scale voltage from the generated gray scale voltages in accordance with display data, for applying inversion/non-inversion control to the selected gray scale voltage with respect to an inversion reference voltage on the basis of the selected gray scale voltage, an AC switching signal and the inversion reference voltage, and for outputting different liquid crystal supply voltages for one and the same display data to a liquid crystal panel.
摘要翻译：液晶驱动器包括：基于参考电压产生灰度电压的电压发生器;以及用于根据显示数据从产生的灰度级电压中选择一个灰度级电压的输出装置，用于施加反相/非反相控制基于所选择的灰度级电压，AC开关信号和反转参考电压相对于反转参考电压的所选择的灰度级电压，并且将用于一个和相同显示数据的不同液晶电源电压输出到液晶面板。

10. 发明申请

US20110038194A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20110038194A1
公开(公告)日：2011-02-17
申请号：US12855151
申请日：2010-08-12
申请人： Takeshi MURATA , Yutaka Ishibashi , Hiroyuki Nitta
发明人： Takeshi MURATA , Yutaka Ishibashi , Hiroyuki Nitta
IPC分类号： G11C5/06 , G11C11/00
CPC分类号： G11C5/063 , G11C11/22 , G11C13/0007 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021
摘要： According to one embodiment, a semiconductor storage device includes a plurality of parallel first interconnects extending in a first direction, a plurality of parallel second interconnects which extend in a second direction perpendicular to the first direction and which make a two-level crossing with respect to the first interconnects, and memory cell structures provided in regions where the first interconnects and the second interconnects make two-level crossings, the memory cell structures being connected on one end to the first interconnects and connected on the other end to the second interconnects, the memory cell structure including a variable resistive element and a non-ohmic element which are connected in series, wherein the endmost first interconnect is disconnected in at least one portion.
摘要翻译：根据一个实施例，半导体存储装置包括在第一方向上延伸的多个平行的第一互连件，多个平行的第二互连件，其沿与第一方向垂直的第二方向延伸，并且相对于所述第一互连和存储单元结构设置在所述第一互连和所述第二互连构成两级交叉的区域中，所述存储单元结构的一端连接到所述第一互连并在另一端连接到所述第二互连，存储单元结构包括串联连接的可变电阻元件和非欧姆元件，其中最末端的第一互连件在至少一部分中断开。

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