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1. 发明授权

US07354812B2 Multiple-depth STI trenches in integrated circuit fabrication 有权
标题翻译：集成电路制造中的多深STI沟槽
公开(公告)号：US07354812B2
公开(公告)日：2008-04-08
申请号：US10931946
申请日：2004-09-01
申请人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
发明人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
IPC分类号： H01L21/337 , H01L21/8238 , H01L21/8249 , H01L21/336 , H01L21/331 , H01L21/76 , H01L33/00 , H01L29/76 , H01L31/00 , H01L29/00
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译：集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。

2. 发明授权

US07119369B2 FET having epitaxial silicon growth 有权
标题翻译：具有外延硅生长的FET
公开(公告)号：US07119369B2
公开(公告)日：2006-10-10
申请号：US10758059
申请日：2004-01-15
申请人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
发明人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L27/108
CPC分类号： H01L29/66651 , H01L21/76264 , H01L29/0653
摘要： A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.
摘要翻译：场效应晶体管具有体半导体衬底中的沟道区，沟道区的第一侧上的第一源极/漏极区，沟道区的第二侧上的第二源极/漏极区和外延的延伸形成在体半导体衬底上以便从沟道区的每一侧延伸的单晶材料。

3. 发明申请

US20060091479A1 Applying epitaxial silicon in disposable spacer flow 有权
公开(公告)号：US20060091479A1
公开(公告)日：2006-05-04
申请号：US11305597
申请日：2005-12-16
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L29/76
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

4. 发明授权

US06962841B2 Suppression of cross diffusion and gate depletion 有权
公开(公告)号：US06962841B2
公开(公告)日：2005-11-08
申请号：US10659081
申请日：2003-09-10
申请人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
发明人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
IPC分类号： G11C11/412 , H01L21/8238 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104
摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

5. 发明授权

US06784062B2 Transistor formation for semiconductor devices 有权
标题翻译：半导体器件的晶体管形成
公开(公告)号：US06784062B2
公开(公告)日：2004-08-31
申请号：US10162289
申请日：2002-06-03
申请人： Chih-Chen Cho , Zhongze Wang
发明人： Chih-Chen Cho , Zhongze Wang
IPC分类号： H01L218238
CPC分类号： H01L27/11 , H01L21/82345 , H01L21/823842
摘要： A semiconductor fabrication method of forming a pair of transistor gates of opposite conductivity type by partially forming first and second gate stacks comprising an insulation layer, a conductive layer and polysilicon layer for the pair of transistor by removing a portion of the polysilicon layer. The polysilicon layer includes a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants. A first-type conductive transistor gate is formed by, completing the formation of the first gate stack and a second-type conductive transistor gate is formed by completing the formation of the second gate stack separately from the formation of the first-type transistor gate.
摘要翻译：通过部分地形成第一和第二栅极堆叠来形成具有相反导电类型的一对晶体管栅极的半导体制造方法，该第一和第二栅极堆叠通过去除多晶硅层的一部分而包括一对晶体管的绝缘层，导电层和多晶硅层。多晶硅层包括第一导电掺杂剂的主要区域和第二导电掺杂剂的主要区域。通过完成第一栅极堆叠的形成而形成第一导电晶体管栅极，并且通过与第一型晶体管栅极的形成分开完成第二栅极堆叠的形成而形成第二导电晶体管栅极。

6. 发明授权

US06730553B2 Methods for making semiconductor structures having high-speed areas and high-density areas 有权
公开(公告)号：US06730553B2
公开(公告)日：2004-05-04
申请号：US09945077
申请日：2001-08-30
申请人： Chih-Chen Cho , Zhongze Wang
发明人： Chih-Chen Cho , Zhongze Wang
IPC分类号： H01L218234
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/105 , H01L27/1052 , H01L27/11
摘要： Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce horizontal resistance, and inhibit cross-diffusion.

7. 发明授权

US06716687B2 FET having epitaxial silicon growth 有权
标题翻译：具有外延硅生长的FET
公开(公告)号：US06716687B2
公开(公告)日：2004-04-06
申请号：US10073723
申请日：2002-02-11
申请人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
发明人： Zhongze Wang , Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L2184
CPC分类号： H01L29/66651 , H01L21/76264 , H01L29/0653
摘要： Field-effect transistors, and methods of their fabrication, having channel regions formed separately from their source/drain regions and having monocrystalline material interposed between the channel regions and the source/drain regions. The monocrystalline material includes monocrystalline silicon and silicon-germanium alloy.
摘要翻译：场效应晶体管及其制造方法具有与其源/漏区分开形成的沟道区，并且具有介于沟道区和源/漏区之间的单晶材料。单晶材料包括单晶硅和硅 - 锗合金。

8. 发明授权

US06448129B1 Applying epitaxial silicon in disposable spacer flow 有权
公开(公告)号：US06448129B1
公开(公告)日：2002-09-10
申请号：US09490261
申请日：2000-01-24
申请人： Chih-Chen Cho , Er-Xuan Ping
发明人： Chih-Chen Cho , Er-Xuan Ping
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/28525 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L27/105 , H01L27/10873 , H01L27/11526 , H01L27/11546 , H01L29/66636
摘要： A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

9. 发明授权

US06218311B1 Post-etch treatment of a semiconductor device 有权
标题翻译：半导体器件的蚀刻后处理
公开(公告)号：US06218311B1
公开(公告)日：2001-04-17
申请号：US09334992
申请日：1999-06-17
申请人： Jeffrey A. McKee , Ming J. Hwang , Chih-Chen Cho , William R. McKee
发明人： Jeffrey A. McKee , Ming J. Hwang , Chih-Chen Cho , William R. McKee
IPC分类号： H01L21302
CPC分类号： H01L29/4941 , H01L21/28123 , H01L21/28176
摘要： Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (48, 148) over an oxidizable section (18, 118) of the semiconductor device. The protective cover (48, 148) is operable to at least inhibit oxidation of the oxidizable section (18, 118). While the oxidizable section (18, 118) is covered, an oxide structure (52, 152) is formed. The oxide structure (52, 152) is operable to at least ameliorate etch damage to the semiconductor device.
摘要翻译：蚀刻损坏的半导体器件的蚀刻后处理包括在半导体器件的可氧化部分（18,118）上形成保护盖（48,148）。保护罩（48,148）可操作以至少抑制可氧化部分（18,118）的氧化。当可氧化部分（18,118）被覆盖时，形成氧化物结构（52,152）。氧化物结构（52,152）可操作以至少改善对半导体器件的蚀刻损伤。

10. 发明授权

US5824603A Method of forming a low-K layer in an integrated circuit 失效
标题翻译：在集成电路中形成低K层的方法
公开(公告)号：US5824603A
公开(公告)日：1998-10-20
申请号：US483422
申请日：1995-06-07
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： H01L21/02 , H01L21/311 , H01L21/312 , H01L21/302
CPC分类号： H01L28/40 , H01L21/31138 , H01L21/312 , Y10S428/901 , Y10T428/24917 , Y10T428/3154 , Y10T428/31544
摘要： This is a device and method of forming such, wherein the device has an amorphous "TEFLON" (TFE AF) layer. The device comprising: a substrate; a TFE AF 44 layer on top of the substrate; and a semiconductor layer 42 on top of the TFE AF 44 layer. The device may be an electronic or optoelectronic device. The semiconductor layer may be a metal or other substance.
摘要翻译：这是一种形成这种装置和方法，其中该装置具有非晶“TEFLON”（TFE AF）层。该装置包括：基板; TFE AF 44层; 以及在TFE AF 44层的顶部上的半导体层42。该装置可以是电子或光电子装置。半导体层可以是金属或其它物质。

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