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1. 发明授权

US5290709A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5290709A
公开(公告)日：1994-03-01
申请号：US865961
申请日：1992-04-09
申请人： Akira Sato
发明人： Akira Sato
IPC分类号： H01L21/265 , H01L21/266 , H01L21/426
CPC分类号： H01L21/266 , Y10S148/076 , Y10S148/082 , Y10S148/083
摘要： According to the present invention, in the ion implantation step in manufacturing a semiconductor device, a resist of a resist pattern formed on a portion of a semiconductor wafer is removed from the outer peripheral portion of the semiconductor wafer, and ion implantation is performed through the resist pattern.Since the resist is removed from the outer peripheral portion, a contact portion between a semiconductor wafer fixing portion of an ion implantation unit and the semiconductor wafer is conductive. Therefore, charges generated by the ion implantation escape from the wafer fixing portion, and the semiconductor wafer is not charged, thereby preventing electrostatic breakdown.
摘要翻译：根据本发明，在制造半导体器件的离子注入步骤中，从半导体晶片的外周部分去除形成在半导体晶片的一部分上的抗蚀剂图案的抗蚀剂，并且通过抗蚀图案由于抗蚀剂从外周部分去除，离子注入单元的半导体晶片固定部分和半导体晶片之间的接触部分是导电的。因此，由离子注入产生的电荷从晶片固定部分逸出，并且半导体晶片不被充电，从而防止静电击穿。

2. 发明授权

US4801555A Double-implant process for forming graded source/drain regions 失效
标题翻译：用于形成分级源极/漏极区域的双注入工艺
公开(公告)号：US4801555A
公开(公告)日：1989-01-31
申请号：US3176
申请日：1987-01-14
申请人： Patrick J. Holly , Louis C. Parrillo , Frank K. Baker
发明人： Patrick J. Holly , Louis C. Parrillo , Frank K. Baker
IPC分类号： H01L21/265
CPC分类号： H01L21/26513 , Y10S148/082 , Y10S148/083
摘要： A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high energy and/or low mass ions to form the deeper grading region. The second implant is a high does implant with low energy and/or high mass ions to form the shallower, lower resistivity source/drain region. Without the optional drive-in step, virtually no lateral grading takes place, resulting in little encroachment of the grading region under the gate. The use of a drive-in step between the two implant steps causes diffusion of the grading dopant, which increases the grading both laterally and vertically, resulting in better breakdown and capacitance characteristics, but increased encroachment under the gate. The present invention allows control over the lateral and vertical grading separately to optimize the trade-offs for a particular application.
摘要翻译：用于在半导体器件中形成分级源极/漏极区域的方法包括两个离子注入步骤和可选的驱入步骤。第一次植入是具有高能量和/或低质量离子的低剂量植入物以形成较深的分级区域。第二种植入物是具有低能量和/或高质量离子的植入物，以形成较浅的较低电阻率源极/漏极区域。没有可选的驱动步骤，几乎没有发生横向分级，导致栅极下方的分级区域几乎不受侵蚀。在两个植入步骤之间的驱动步骤的使用导致分级掺杂剂的扩散，这增加了横向和垂直的分级，导致更好的击穿和电容特性，但增加了栅极下的侵蚀。本发明允许单独控制横向和垂直分级以优化特定应用的权衡。

3. 发明授权

US4631570A Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection 失效
标题翻译：具有埋置氧化物隔离的集成电路和用于电源互连的低电阻衬底
公开(公告)号：US4631570A
公开(公告)日：1986-12-23
申请号：US628019
申请日：1984-07-03
申请人： Mark S. Birrittella , Robert H. Reuss , Walter C. Seelbach
发明人： Mark S. Birrittella , Robert H. Reuss , Walter C. Seelbach
IPC分类号： H01L27/04 , H01L21/762 , H01L21/822 , H01L21/8222 , H01L23/528 , H01L27/06 , H01L27/082 , H01L27/12 , H01L27/02
CPC分类号： H01L21/76243 , H01L23/5286 , H01L27/0825 , H01L2924/0002 , Y10S148/083 , Y10S148/085 , Y10S257/906
摘要： An integrated circuit power supply interconnection technique is disclosed having a highly doped, low resistivity substrate for distribution of the integrated circuit's most positive supply voltage. The substrate functions as the most positive voltage point and accomodates devices that are normally connected directly to this most positive supply voltage. A dielectric buried layer overlies a portion of the substrate and isolates the substrate supply voltage from devices that are not connected directly to the most positive supply voltage.
摘要翻译：公开了一种集成电路电源互连技术，其具有用于分配集成电路最正电源电压的高掺杂的低电阻率衬底。衬底作为最正的电压点，并且适应通常直接连接到最正电源电压的器件。电介质掩埋层覆盖在衬底的一部分上，并将衬底电源电压与不直接连接到最正电源电压的器件隔离。

4. 发明授权

US4574469A Process for self-aligned buried layer, channel-stop, and isolation 失效
标题翻译：自对准埋层，通道停止和隔离的工艺
公开(公告)号：US4574469A
公开(公告)日：1986-03-11
申请号：US650964
申请日：1984-09-14
申请人： Sal Mastroianni , Carroll Casteel , Terry S. Hulseweh
发明人： Sal Mastroianni , Carroll Casteel , Terry S. Hulseweh
IPC分类号： H01L21/762 , H01L21/76 , H01L21/223 , H01L21/31 , H01L21/74
CPC分类号： H01L21/76216 , Y10S148/035 , Y10S148/083 , Y10S148/086 , Y10S148/117 , Y10S148/122 , Y10S438/969
摘要： A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a non-single crystal semiconductor region, above a doped channel-stop region. A single mask layer determines the location and spacing of the non-single crystal portion of the isolation walls, the channel-stops, and the buried layers.
摘要翻译：描述了用于在公共衬底中制造隔离半导体器件的工艺，其具有自对准和预定位的隔离壁，掩埋层和通道停止。隔离壁由掺杂的通道阻挡区域上方的电介质区域和非单晶半导体区域的堆叠布置形成。单个掩模层确定隔离壁的非单晶部分，通道停止部和掩埋层的位置和间隔。

5. 发明授权

US4569124A Method for forming thin conducting lines by ion implantation and preferential etching 失效
标题翻译：通过离子注入和优先蚀刻形成薄导线的方法
公开(公告)号：US4569124A
公开(公告)日：1986-02-11
申请号：US613114
申请日：1984-05-22
申请人： David B. Rensch , John Y. Chen
发明人： David B. Rensch , John Y. Chen
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/3213 , H01L21/3215 , H01L21/336 , H01L21/338 , H01L21/302 , H01L21/425
CPC分类号： H01L29/66863 , H01L21/32134 , H01L21/32136 , H01L21/32137 , H01L21/3215 , H01L21/32155 , H01L29/66575 , Y10S148/019 , Y10S148/083 , Y10S148/147 , Y10S438/942
摘要： A thin conducting line such as a gate pattern is defined on a semiconductor chip (10) by applying a narrow ion beam, suitably a focused-ion-beam (16) having a submicrometer thickness from a source (18) onto a thin layer (14) of an inorganic material such as silicon or aluminum overlying a layer (12) of refractory metal on a substrate (11). The ion beam is translated to form a gate pattern at a dose between about 0.1 to 50.times.10.sup.15 cm.sup.-2 and an energy from about 1 to 1000 KeV. Ions are implanted into the silicon and aluminum layers and into the underlying portions of the refractory metal layer and to render the exposed portions of the layers preferentially resistant to wet-etchant. The portions of layers which are not exposed nor protected by layers which are exposed, are preferentially removed to form a gate. Conventional MOSFET or MESFET processing to implant ions to form source and drain regions may then be performed.
摘要翻译：通过将窄离子束（适当地是具有亚微米厚度的聚焦离子束（16））从源（18）施加到薄层（10）上而限定在半导体芯片（10）上的薄导线 14）覆盖在基底（11）上的难熔金属层（12）上的无机材料，例如硅或铝。将离子束平移以在约0.1至50×10 15 cm -2之间的剂量和约1至1000KeV的能量下形成栅极图案。离子被植入到硅和铝层中并进入难熔金属层的下面部分，并且使得这些层的暴露部分优先抵抗湿蚀刻剂。优选地除去未暴露的层的不暴露的层的部分以形成栅极。然后可以执行用于注入离子以形成源区和漏区的常规MOSFET或MESFET处理。

6. 发明授权

US3388009A Method of forming a p-n junction by an ionic beam 失效
标题翻译：通过离子束形成p-n结的方法
公开(公告)号：US3388009A
公开(公告)日：1968-06-11
申请号：US46621865
申请日：1965-06-23
申请人： ION PHYSICS CORP
发明人： KING WILLIAM J
IPC分类号： H01J37/317 , H01L21/00 , H01L21/265
CPC分类号： H01L21/2652 , H01J37/3171 , H01L21/00 , Y10S148/083

7. 发明授权

US5294557A Implanting impurities in semiconductors and semiconductor implanted with impurities 失效
标题翻译：在半导体中植入杂质和注入杂质的半导体
公开(公告)号：US5294557A
公开(公告)日：1994-03-15
申请号：US749825
申请日：1991-08-26
申请人： Frederick G. Moore , Harry B. Dietrich
发明人： Frederick G. Moore , Harry B. Dietrich
IPC分类号： H01L21/265
CPC分类号： H01L21/26546 , Y10S148/056 , Y10S148/083 , Y10S148/084
摘要： A method for ion-implanting a dopant species in semiconductors includes the steps of implanting a dopant species in a semiconductor material at a predetermined rate, the predetermined rate being based on a rate corresponding to a maximum in a characteristic graph of percent activation as a function of dopant species implantation rate; and annealing the dopant implanted semiconductor.
摘要翻译：用于在半导体中离子注入掺杂剂物质的方法包括以预定速率将掺杂剂物质注入到半导体材料中的步骤，预定速率基于与激活百分比作为函数的特征图中的最大值相对应的速率的掺杂物种植率; 并对掺杂剂注入的半导体进行退火。

8. 发明授权

US5244820A Semiconductor integrated circuit device, method for producing the same, and ion implanter for use in the method 失效
标题翻译：半导体集成电路装置及其制造方法以及该方法中使用的离子注入机
公开(公告)号：US5244820A
公开(公告)日：1993-09-14
申请号：US921988
申请日：1992-08-03
申请人： Tadashi Kamata , Mitsuharu Honda , Jun Sugiura , Nobuo Owada , Hizuru Yamaguchi
发明人： Tadashi Kamata , Mitsuharu Honda , Jun Sugiura , Nobuo Owada , Hizuru Yamaguchi
IPC分类号： H01L21/265 , H01L21/8242
CPC分类号： H01L21/26593 , H01L21/265 , H01L21/26506 , H01L21/26513 , H01L21/2652 , H01J2237/2001 , H01J2237/31701 , H01L27/10894 , Y10S148/083
摘要： The present invention relates to an ion implantation process in a wafer process for a semiconductor integrated circuit device. Particularly, according to the present invention, a shallow junction can be formed by performing the implantation of ion while holding a wafer to be processed at a low temperature.
摘要翻译：本发明涉及用于半导体集成电路器件的晶片工艺中的离子注入工艺。特别地，根据本发明，可以通过在保持待处理的晶片在低温下进行离子的注入来形成浅结。

9. 发明授权

US5023191A Method of producing a semiconductor device using a single mask method for providing multiple masking patterns 失效
标题翻译：使用单掩模方法制造半导体器件以提供多种掩模图案的方法
公开(公告)号：US5023191A
公开(公告)日：1991-06-11
申请号：US444567
申请日：1989-12-01
申请人： Kenya Sakurai
发明人： Kenya Sakurai
IPC分类号： H01L29/78 , H01L21/331 , H01L21/336 , H01L29/10 , H01L29/739
CPC分类号： H01L29/66712 , H01L29/1095 , H01L29/66333 , Y10S148/082 , Y10S148/083 , Y10S438/943
摘要： A single mask method for providing multiple masking patterns, using excess etching techniques, which is usable for developing a semiconductor substrate for a semiconductor device which results in an increased current being required before latchup occurs in the semiconductor device.
摘要翻译：一种用于提供多个掩模图案的单一掩模方法，其使用多余的蚀刻技术，其可用于在半导体器件中发生闭锁之前导致需要增加的电流的半导体器件的半导体衬底。

10. 发明授权

US4937206A Method and apparatus for preventing cross contamination of species during the processing of semiconductor wafers 失效
标题翻译：在半导体晶片加工过程中防止物种交叉污染的方法和装置
公开(公告)号：US4937206A
公开(公告)日：1990-06-26
申请号：US377692
申请日：1989-07-10
申请人： Peter R. Jaffe , Kevin Fairbairn
发明人： Peter R. Jaffe , Kevin Fairbairn
IPC分类号： H01J37/20 , H01J37/317 , H01L21/265 , H01L21/266 , H01L21/302
CPC分类号： H01L21/302 , H01L21/265 , Y10S148/083 , Y10S438/905 , Y10S438/908 , Y10T29/41
摘要： A method for preventing cross-contamination of semiconductor wafers during processing comprising covering a surface portion of a support assembly with a process compatible material, engaging a semiconductor wafer with the support assembly, processing the wafer while it is engaged with the support member, and removing the process compatible material from the support assembly after said material is considered to be contaminated. A shield particularly adapted for this process includes a shield portion made from a process compatible material and a process-compatible adhesive for attaching the shield portion to the support assembly.

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