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1. 发明授权

US5290709A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5290709A
公开(公告)日：1994-03-01
申请号：US865961
申请日：1992-04-09
申请人： Akira Sato
发明人： Akira Sato
IPC分类号： H01L21/265 , H01L21/266 , H01L21/426
CPC分类号： H01L21/266 , Y10S148/076 , Y10S148/082 , Y10S148/083
摘要： According to the present invention, in the ion implantation step in manufacturing a semiconductor device, a resist of a resist pattern formed on a portion of a semiconductor wafer is removed from the outer peripheral portion of the semiconductor wafer, and ion implantation is performed through the resist pattern.Since the resist is removed from the outer peripheral portion, a contact portion between a semiconductor wafer fixing portion of an ion implantation unit and the semiconductor wafer is conductive. Therefore, charges generated by the ion implantation escape from the wafer fixing portion, and the semiconductor wafer is not charged, thereby preventing electrostatic breakdown.
摘要翻译：根据本发明，在制造半导体器件的离子注入步骤中，从半导体晶片的外周部分去除形成在半导体晶片的一部分上的抗蚀剂图案的抗蚀剂，并且通过抗蚀图案由于抗蚀剂从外周部分去除，离子注入单元的半导体晶片固定部分和半导体晶片之间的接触部分是导电的。因此，由离子注入产生的电荷从晶片固定部分逸出，并且半导体晶片不被充电，从而防止静电击穿。

2. 发明申请

US20020162608A1 Medical implant made of biocompatible low modulus high strength titanium-niobium alloy and method of using the same 失效
标题翻译：由生物相容性低模量高强度钛铌合金制成的医用植入物及其使用方法
公开(公告)号：US20020162608A1
公开(公告)日：2002-11-07
申请号：US10134524
申请日：2002-04-30
发明人： Jiin-Huey Chern Lin , Chien-Ping Ju , Chih-Min Lee
IPC分类号： C22C014/00
CPC分类号： C22C14/00 , A61L27/06 , Y10S148/076
摘要： A biocompatible binary titanium-niobium (TinullNb) alloy having a low modulus and a high strength, and containing nullnull phase as a major phase is disclosed. The binary TinullNb alloy contains 10-30 wt % of Nb, preferably 13-28 wt % of Nb, and the balance titanium, which is suitable for making a medical implant such as an orthopedic implant or dental implant.
摘要翻译：公开了具有低模量和高强度并且包含α相作为主相的生物相容性二元钛铌（Ti-Nb）合金。二元Ti-Nb合金含有10-30重量％的Nb，优选Nb为13-28重量％，余量钛适用于制造医疗植入物如矫形植入物或牙科植入物。

3. 发明授权

US5314839A Solid state device fabrication method including a surface treatment step with a neutral particle beam with an energy between 10ev and 100ev 失效
标题翻译：固态器件制造方法包括具有10ev至100ev之间能量的中性粒子束的表面处理步骤
公开(公告)号：US5314839A
公开(公告)日：1994-05-24
申请号：US756274
申请日：1991-09-06
申请人： Tatsumi Mizutani , Takashi Yunogami , Kenetsu Yokokawa , Nobuyoshi Kobayashi
发明人： Tatsumi Mizutani , Takashi Yunogami , Kenetsu Yokokawa , Nobuyoshi Kobayashi
IPC分类号： H01L21/00 , H01L21/3105 , H01L21/314 , H01L21/316 , H01L21/26
CPC分类号： H01L21/67132 , H01L21/3105 , H01L21/314 , Y10S148/076
摘要： To improve the characteristics of oxides and other insulators formed by conventional techniques, particularly to improve its density, relative dielectric constant, resistance to acid, resistance to reduction and other characteristics, and to provide solid state devices or socharacteristics, the surfaces of the silicon oxide insulator, or the like, is irradiated with electrically neutral particles.
摘要翻译：为了改善通过常规技术形成的氧化物和其它绝缘体的特性，特别是提高其密度，相对介电常数，耐酸性，耐还原性等特性，以及提供固态器件或特性，氧化硅表面绝缘体等被电中性粒子照射。

4. 发明授权

US5804471A Method of fabricating thin film transistor 失效
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US5804471A
公开(公告)日：1998-09-08
申请号：US657109
申请日：1996-06-03
申请人： Shunpei Yamazaki , Akira Takenouchi , Yasuhiko Takemura
发明人： Shunpei Yamazaki , Akira Takenouchi , Yasuhiko Takemura
IPC分类号： H01L21/205 , H01L21/265 , H01L21/268 , H01L21/302 , H01L21/3065 , H01L21/336 , H01L21/77 , H01L21/84 , H01L21/00
CPC分类号： H01L21/2026 , H01L21/2022 , H01L21/268 , H01L27/1214 , H01L29/66757 , Y10S148/076 , Y10S148/09 , Y10S438/913
摘要： A multi-chamber system for providing a process of a high degree of cleanliness in fabricating semiconductor devices such as semiconductor integrated circuits. The system comprises a plurality of vacuum apparatus (e.g., a film formation apparatus, an etching apparatus, a thermal processing apparatus, and a preliminary chamber) for fabrication of semiconductor devices. At least one of these vacuum apparatuses is a laser.
摘要翻译：一种用于在制造半导体集成电路的半导体器件中提供高度清洁度的工艺的多室系统。该系统包括用于制造半导体器件的多个真空装置（例如，成膜装置，蚀刻装置，热处理装置和预备室）。这些真空装置中的至少一个是激光。

5. 发明授权

US4611388A Method of forming an indium phosphide-boron phosphide heterojunction bipolar transistor 失效
标题翻译：形成磷化铟 - 磷化氢异质结双极晶体管的方法
公开(公告)号：US4611388A
公开(公告)日：1986-09-16
申请号：US723423
申请日：1985-04-15
申请人： Krishna P. Pande
发明人： Krishna P. Pande
IPC分类号： H01L21/205 , H01L21/331 , H01L29/205 , H01L29/73 , H01L21/20 , H01L21/265
CPC分类号： H01L29/66318 , H01L21/02392 , H01L21/02543 , H01L21/0262 , H01L29/205 , H01L29/73 , Y10S148/065 , Y10S148/072 , Y10S148/076 , Y10S148/084 , Y10S148/11 , Y10S148/119
摘要： A heterojunction bipolar transistor having an n- type epitaxial indium phosphide collector layer grown on a semi-insulating indium phosphide substrate with an n+ buried layer, a p- type indium phosphide base and an epitaxial, n- type boron phosphide wide gap emitter. The p- type base region is formed by ion implantation of magnesium ions into the collector layer. The transistor is applicable to millimeter wave applications due to the high electron mobility in the indium phosphide base. The wide gaps of both the boron phosphide (2.2 eV) and indium phosphide (1.34 eV) permit operation up to 350.degree. C. The transistor is easily processed using metal organic-chemical vapor deposition (MO-CVD) and standard microelectronic techniques.
摘要翻译：一种异质结双极晶体管，其具有在具有n +掩埋层，p-型磷化铟基底和外延，n-型磷化硼宽间隙发射体的半绝缘磷化铟衬底上生长的n型外延铟磷化物集电极层。 p型基极区通过将镁离子离子注入到集电极层中而形成。由于磷化铟基底中的高电子迁移率，晶体管适用于毫米波应用。硼化磷（2.2eV）和磷化铟（1.34eV）的宽间隙允许在350℃下工作。使用金属有机 - 化学气相沉积（MO-CVD）和标准微电子技术容易地处理晶体管。

6. 发明授权

US06752882B2 Medical implant made of biocompatible low modulus high strength titanium-niobium alloy and method of using the same 失效
标题翻译：由生物相容性低模量高强度钛铌合金制成的医用植入物及其使用方法
公开(公告)号：US06752882B2
公开(公告)日：2004-06-22
申请号：US10134524
申请日：2002-04-30
申请人： Jiin-Huey Chern Lin , Chien-Ping Ju , Chih-Min Lee
发明人： Jiin-Huey Chern Lin , Chien-Ping Ju , Chih-Min Lee
IPC分类号： C22C1400
CPC分类号： C22C14/00 , A61L27/06 , Y10S148/076
摘要： A biocompatible binary titanium-niobium (Ti—Nb) alloy having a low modulus and a high strength, and containing &agr;″ phase as a major phase is disclosed. The binary Ti—Nb alloy contains 10-30 wt % of Nb, preferably 13-28 wt % of Nb, and the balance titanium, which is suitable for making a medical implant such as an orthopedic implant or dental implant.
摘要翻译：公开了具有低模量和高强度并且包含α相作为主相的生物相容性二元钛铌（Ti-Nb）合金。二元Ti-Nb合金含有10-30重量％的Nb，优选Nb为13-28重量％，余量钛适用于制造医疗植入物如矫形植入物或牙科植入物。

7. 发明授权

US06409852B1 Biocompatible low modulus titanium alloy for medical implant 有权
标题翻译：用于医疗植入物的生物相容性低模量钛合金
公开(公告)号：US06409852B1
公开(公告)日：2002-06-25
申请号：US09226204
申请日：1999-01-07
申请人： Jiin-Huey Chern Lin , Chien-Ping Ju , Wen-Fu Ho
发明人： Jiin-Huey Chern Lin , Chien-Ping Ju , Wen-Fu Ho
IPC分类号： C22F118
CPC分类号： C22C14/00 , A61L27/06 , Y10S148/076
摘要： A biocompatible titanium alloy with low modulus comprising &agr;″ phase as a major phase and containing from about 6 to about 9 wt % of molybdenum, from 0 to about 1 wt % of an alloying element and the balance titanium. The alloying element is niobium and/or zirconium. The biocompatible titanium alloy is suitable for use as a material for a medical prosthetic implant.
摘要翻译：具有低模量的生物相容性钛合金，其包含α相作为主相，并且含有约6至约9重量％的钼，0至约1重量％的合金元素和余量钛。合金元素是铌和/或锆。生物相容性钛合金适用于医用假体植入物的材料。

8. 发明授权

US5082793A Method for making solid state device utilizing ion implantation techniques 失效
标题翻译：利用离子注入技术制作固态器件的方法
公开(公告)号：US5082793A
公开(公告)日：1992-01-21
申请号：US438692
申请日：1989-11-17
申请人： Chou H. Li
发明人： Chou H. Li
IPC分类号： C30B21/02 , C30B21/04 , H01L21/24 , H01L21/76 , H01L21/761 , H01L21/762 , H01L21/763 , H01L21/764 , H01L27/00 , H01L27/142 , H01L27/144 , H01L27/15 , H01L29/04 , H01L29/06 , H01L31/00 , H01L31/036 , H01L31/0687 , H01L31/078 , H01L31/18 , H01L33/18 , H01L33/24
CPC分类号： H01L31/18 , C30B21/02 , C30B21/04 , H01L21/24 , H01L21/76 , H01L21/761 , H01L21/762 , H01L21/763 , H01L21/764 , H01L27/00 , H01L27/142 , H01L27/1446 , H01L27/156 , H01L29/04 , H01L29/0657 , H01L29/0661 , H01L31/00 , H01L31/036 , H01L31/0687 , H01L31/078 , H01L33/18 , H01L33/24 , Y02E10/544 , Y02P70/521 , Y10S148/076 , Y10S148/083 , Y10S148/085 , Y10S148/117 , Y10S438/938
摘要： A method of making a dielectric isolation integrated circuit structure in which dielectric material grooves formed by ion implantation extend down into the structure and intersect a PN junction or other active region at intersection lines such that each intersection line is within microns both laterally from the center of the groove and vertically from the bottom of the groove and the grooves continuously curve at least at the intersection lines at a radius of curvature less than 1 cm.
摘要翻译：一种制造绝缘隔离集成电路结构的方法，其中通过离子注入形成的电介质材料槽向下延伸到结构中，并且在交叉线处与PN结或其它有源区相交，使得每个交叉线在两边以内的微米内槽和槽的底部垂直并且凹槽至少在相交线处以小于1cm的曲率半径连续弯曲。

9. 发明授权

US4885257A Gettering process with multi-step annealing and inert ion implantation 失效
标题翻译：吸收过程采用多步退火和惰性离子注入
公开(公告)号：US4885257A
公开(公告)日：1989-12-05
申请号：US57672
申请日：1987-06-02
申请人： Yoshiaki Matsushita
发明人： Yoshiaki Matsushita
IPC分类号： H01L21/70 , H01L21/20 , H01L21/322 , H01L21/8242 , H01L27/00 , H01L27/10 , H01L27/108 , H01L29/167
CPC分类号： H01L29/167 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/322 , H01L21/3221 , Y10S148/003 , Y10S148/024 , Y10S148/06 , Y10S148/076 , Y10S148/083 , Y10S148/097 , Y10S148/127
摘要： A semiconductor substrate and process for making are disclosed. The substrate is suitable for use in manufacturing large scale integrated circuits. The process comprises the steps of heating a semiconductor substrate at a temperature not lower than 1100.degree. C., implanting electrically inert impurities into the major surface of the substrate, heating the substrate at a temperature ranging from 600.degree. to 900.degree. C. and providing a single crystal semiconductor layer.
摘要翻译：公开了一种半导体衬底及其制造方法。该基板适用于制造大规模集成电路。该方法包括以下步骤：在不低于1100℃的温度下加热半导体衬底，将电惰性杂质注入衬底的主表面，在600-900℃的温度范围内加热衬底，并提供单晶半导体层。

10. 发明授权

US4555273A Furnace transient anneal process 失效
标题翻译：炉式瞬态退火工艺
公开(公告)号：US4555273A
公开(公告)日：1985-11-26
申请号：US583560
申请日：1984-02-27
申请人： David A. Collins , Derek L. Lile , Carl R. Zeisse
发明人： David A. Collins , Derek L. Lile , Carl R. Zeisse
IPC分类号： H01L21/00 , H01L21/324 , H01L21/265
CPC分类号： H01L21/67109 , Y10S148/003 , Y10S148/006 , Y10S148/071 , Y10S148/076
摘要： A method for annealing semiconductor samples, especially following ion-implantation of semiconductor samples is disclosed. A furnace on a set of rails is passed over the semiconductor sample which is supported on a stationary wire basket made of low thermal mass, fine tungsten wire. The furnace temperature may be about 5.degree. above the desired anneal temperature of the semiconductor sample such that the sample temperature rises to within a few degrees of the furnace temperature within seconds. Utilizing the moveable furnace insures uniform heating without elaborate temperature control or expensive beam generating equipment.The apparatus and process of the present invention are utilized for rapid annealing of ion-implanted indium phosphide semiconductors within 10 to 30 seconds and at temperatures of approximately 700.degree. C., thereby eliminating undesired and damaging movement of impurities within the ion-implanted InP.
摘要翻译：公开了一种用于半导体样品退火的方法，特别是在半导体样品的离子注入之后。在一组轨道上的炉子通过半导体样品，该半导体样品被支撑在由低热质量的精细钨丝制成的固定丝网上。炉温可以比半导体样品的期望退火温度高约5℃，使得样品温度在几秒钟内升高到炉温的几度之内。利用可移动炉确保均匀的加热，无需精细的温度控制或昂贵的光束产生设备。本发明的设备和方法用于离子注入的磷化铟半导体在10-30秒内和约700℃的温度下进行快速退火，从而消除离子注入的InP中杂质的不期望的和有害的运动。

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