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1. 发明授权

US5625209A Silicon based sensor apparatus 失效
标题翻译：硅基传感器装置
公开(公告)号：US5625209A
公开(公告)日：1997-04-29
申请号：US434816
申请日：1995-05-04
申请人： Mark Appleton , William R. Krenik
发明人： Mark Appleton , William R. Krenik
IPC分类号： G01N27/12 , H01L23/58
CPC分类号： G01N27/12 , Y10S148/035 , Y10S148/052
摘要： A biomedical sensor (20) is formed on a semiconductor substrate (22). Insulated dielectric layers (23, 24) are formed on the face and backside of the semiconductor substrate (22). Metal leads (26, 28) contact the substrate (22) through openings in the dielectric layer (23). The leads (26, 28) are also each connected to a set of interleaved longitudinal contact fingers (27, 29). A pair of contacts (30, 32) are formed on the opposite side of the substrate (22) from the contact figures (27, 29). A conductive biologic sample is placed over the interleaf fingers (27, 29), electrical measurements can be made through backside contacts (30, 32) so resistance measurements can be taken.
摘要翻译：生物医学传感器（20）形成在半导体衬底（22）上。绝缘电介质层（23,24）形成在半导体衬底（22）的表面和背面上。金属引线（26,28）通过介电层（23）中的开口接触基板（22）。引线（26,28）也各自连接到一组交错的纵向接触指（27,29）。一对触点（30,32）形成在基板（22）的与接触图（27,29）相反的一侧上。将导电生物样品放置在中间指状物（27,29）上，可以通过背侧触点（30,32）进行电气测量，因此可以进行电阻测量。

2. 发明授权

US5587326A Method of forming bipolar junction transistor of epitaxial planar type 失效
标题翻译：形成外延平面型双极结型晶体管的方法
公开(公告)号：US5587326A
公开(公告)日：1996-12-24
申请号：US965027
申请日：1992-10-23
申请人： Hisashi Takemura
发明人： Hisashi Takemura
IPC分类号： H01L29/73 , H01L21/225 , H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/2257 , Y10S148/01 , Y10S148/011 , Y10S148/035 , Y10S148/124
摘要： In a bipolar junction transistor of an epitaxial planar type comprising a base region, an emitter region formed in the base region, and a poly-silicon layer as an emitter poly-silicon electrode layer overlying the emitter region, the poly-silicon layer being used as an impurity diffusion source for forming the emitter region in fabrication of the transistor, the emitter poly-silicon electrode layer comprises a poly-silicon film containing an additive of one of C, O, and P overlying the emitter region and a poly-silicon layer overlying the poly-silicon film. An impurity is doped in the poly-silicon layer and is diffused into the base region through the poly-silicon film to form the emitter region in the base region in fabrication of the transistor. The poly-silicon film contains the additive and serves to prevent the poly-silicon film and the poly-silicon layer from grain growth which badly affects the impurity diffusion for forming the emitter region.
摘要翻译：在包括基极区域的基极区域形成的外延平面型双极结型晶体管中，形成在基极区域中的发射极区域和覆盖发射极区域的多晶硅层作为发射极多晶硅电极层，使用多晶硅层作为用于在晶体管制造中形成发射极区域的杂质扩散源，发射极多晶硅电极层包括含有覆盖发射极区域的C，O和P之一的添加剂的多晶硅膜和多晶硅层叠在多晶硅膜上。在多晶硅层中掺杂杂质，并通过多晶硅膜扩散到基极区域，以在晶体管的制造中在基极区域中形成发射极区域。多晶硅膜含有添加剂，用于防止多晶硅膜和多晶硅层的晶粒生长，严重影响用于形成发射极区域的杂质扩散。

3. 发明授权

US5494852A High capacity semiconductor dopant deposition/oxidization process using a single furnace cycle 失效
标题翻译：使用单炉循环的大容量半导体掺杂剂沉积/氧化过程
公开(公告)号：US5494852A
公开(公告)日：1996-02-27
申请号：US98667
申请日：1993-07-28
申请人： Jon A. Gwin
发明人： Jon A. Gwin
IPC分类号： B01L1/00 , C30B31/06 , H01L21/225 , H01L21/31 , H01L21/385
CPC分类号： H01L21/2255 , C30B31/06 , Y10S148/03 , Y10S148/035
摘要： A semiconductor deposition and oxidation process using a single furnace cycle. The temperature and gas mixture is stabilized inside the furnace prior to introduction of a dopant at a relatively low temperature. The temperature of the chamber is then ramped-up and the dopant is diffused into the wafer in an inert ambient. The temperature is then ramped-up again and oxygen is introduced to produce an oxide layer. The wafers are then removed from the furnace and any residue of the dopant within the chamber is effectively neutralized by introducing a high flow of oxygen.
摘要翻译：使用单炉循环的半导体沉积和氧化工艺。在较低温度下引入掺杂剂之前，温度和气体混合物在炉内稳定。然后，室的温度升高，并且掺杂剂在惰性环境中扩散到晶片中。然后将温度再次升高并引入氧气以产生氧化物层。然后从炉中取出晶片，并通过引入高流量的氧来有效地中和室内的掺杂剂的任何残余物。

4. 发明授权

US4643777A Method of manufacturing a semiconductor device comprising resistors of high and low resistances 失效
标题翻译：制造包括高电阻和低电阻的电阻器的半导体器件的方法
公开(公告)号：US4643777A
公开(公告)日：1987-02-17
申请号：US683479
申请日：1984-12-19
申请人： Takeo Maeda
发明人： Takeo Maeda
IPC分类号： H01L21/3205 , H01L21/02 , H01L23/52 , H01L21/283
CPC分类号： H01L28/24 , Y10S148/035 , Y10S148/105 , Y10S148/147
摘要： There is disclosed a method of manufacturing a semiconductor device comprising the steps of forming a polysilicon film on a semiconductor substrate through an oxidation film, forming a mask of a predetermined pattern on the polysilicon film, forming a molybdenum film on the polysilicon film, and silicifying those regions of said molybdenum film not covered by the mask so that a structure of the uncovered molybdenum film regions and those regions of the polysilicon film located under the uncovered molybdenum regions have low resistance, while a region of the molybdenum film covered by the mask has high resistance.
摘要翻译：公开了一种制造半导体器件的方法，包括以下步骤：通过氧化膜在半导体衬底上形成多晶硅膜，在多晶硅膜上形成预定图案的掩模，在多晶硅膜上形成钼膜，并将硅化物所述钼膜的未被掩模覆盖的那些区域，使得未覆盖的钼膜区域的结构和位于未覆盖的钼区域下方的多晶硅膜的那些区域具有低电阻，而由掩模覆盖的钼膜的区域具有高电阻。

5. 发明授权

US4554728A Simplified planarization process for polysilicon filled trenches 失效
标题翻译：用于多晶硅填充沟槽的简化平面化处理
公开(公告)号：US4554728A
公开(公告)日：1985-11-26
申请号：US624876
申请日：1984-06-27
申请人： Joseph F. Shepard
发明人： Joseph F. Shepard
IPC分类号： H01L21/76 , H01L21/302 , H01L21/3065 , H01L21/3215 , H01L21/763 , H01L21/22
CPC分类号： H01L21/763 , H01L21/32155 , Y10S148/035 , Y10S148/05 , Y10S438/924
摘要： The method of planarizing polysilicon-filled trenches involves first filling the trenches with an undoped polysilicon until the upper surface is substantially planar. The polycrystalline silicon is then heavily doped by means of diffusion of a dopant from the upper surface. The time and temperature of the diffusion are carefully controlled providing for the dopant to penetrate the polysilicon to a depth level with the tops of the trenches. A selective etchant is then utilized which removes the heavily doped polysilicon and leaves the undoped polysilicon untouched in the trenches.
摘要翻译：平坦化多晶硅填充的沟槽的方法包括首先用未掺杂多晶硅填充沟槽，直到上表面基本上是平面的。然后通过来自上表面的掺杂剂的扩散，多晶硅被重掺杂。仔细地控制扩散的时间和温度，使掺杂剂穿透多晶硅至沟槽顶部的深度水平。然后使用选择性蚀刻剂，其去除重掺杂多晶硅并且将未掺杂的多晶硅留在沟槽中。

6. 发明授权

US4203079A Injection lasers 失效
标题翻译：注射激光
公开(公告)号：US4203079A
公开(公告)日：1980-05-13
申请号：US886235
申请日：1978-03-13
申请人： George H. B. Thompson , David F. Lovelace
发明人： George H. B. Thompson , David F. Lovelace
IPC分类号： H01L21/3063 , H01L33/00 , H01S5/00 , H01S5/20 , H01S3/19
CPC分类号： H01L33/0025 , H01S5/20 , H01S5/2059 , Y10S148/035 , Y10S148/051 , Y10S148/072 , Y10S438/923
摘要： Porous silica doped with zinc is used as a p-type dopant source in the construction of rib lasers. Other modifications include allowing the zinc diffusion to go right through the active layer and to dimension the device so that lateral optical guidance is unaffected by the rib.
摘要翻译：掺杂锌的多孔二氧化硅在肋状激光器的构造中用作p型掺杂剂源。其他修改包括允许锌扩散直接穿过有源层并且使器件尺寸使得横向光学引导不受肋的影响。

7. 发明授权

US3602781A Integrated semiconductor circuit comprising only low temperature processed elements 失效
标题翻译：集成半导体电路仅包含低温处理元件
公开(公告)号：US3602781A
公开(公告)日：1971-08-31
申请号：US3602781D
申请日：1969-09-26
申请人： PHILIPS CORP
发明人： HART PAUL ANTON HERMAN
IPC分类号： H01L21/00 , H01L21/82 , H01L27/00 , H01L27/07 , H01L19/00
CPC分类号： H01L27/0761 , H01L21/00 , H01L21/82 , H01L27/00 , H01L27/0716 , Y10S148/007 , Y10S148/035 , Y10S148/085 , Y10S148/139 , Y10S148/15 , Y10S438/98
摘要： An integrated semiconductor is described in which all the interconnected circuit elements, including barrier layers and contacts, comprise only metal-semiconductor junctions, ion implanted junctions, or insulating layers, produced by low temperature processes only, to avoid detrimental effects on a supporting substrate.

8. 发明授权

US3484662A Thin film transistor on an insulating substrate 失效
标题翻译：绝缘基板上的薄膜晶体管
公开(公告)号：US3484662A
公开(公告)日：1969-12-16
申请号：US3484662D
申请日：1968-05-17
申请人： NORTH AMERICAN ROCKWELL
发明人： HAGON PETER J
IPC分类号： H01L21/86 , H01L27/00 , H01L27/06 , H01L27/12 , H01L29/00 , H01L29/73 , H01L11/00 , H01L3/00 , H01L5/00
CPC分类号： H01L29/7317 , H01L21/86 , H01L27/00 , H01L27/0647 , H01L27/12 , H01L29/00 , Y10S148/035 , Y10S148/15

9. 发明授权

US3465215A Process for fabricating monolithic circuits having matched complementary transistors and product 失效
标题翻译：制作具有相应的补充晶体管和产品的单片电路的工艺
公开(公告)号：US3465215A
公开(公告)日：1969-09-02
申请号：US3465215D
申请日：1967-06-30
申请人： TEXAS INSTRUMENTS INC
发明人： BOHANNON RALPH O JR , STEHLIN ROBERT A
IPC分类号： H01L21/761 , H01L21/8228 , H01L27/06 , H01L27/082 , H01L11/00 , H01L7/00
CPC分类号： H01L21/82285 , H01L21/761 , H01L27/0652 , H01L27/0826 , Y10S148/035 , Y10S148/037 , Y10S148/085

10. 发明授权

US5399231A Method of forming crystalline silicon devices on glass 失效
标题翻译：在玻璃上形成晶体硅器件的方法
公开(公告)号：US5399231A
公开(公告)日：1995-03-21
申请号：US137411
申请日：1993-10-18
申请人： Anthony M. McCarthy
发明人： Anthony M. McCarthy
IPC分类号： G02F1/1362 , H01L21/20 , H01L21/306 , B44C1/22 , C03C15/00
CPC分类号： H01L21/2007 , G02F1/13454 , H01L27/1214 , H01L27/1266 , Y10S148/035
摘要： A method for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics.
摘要翻译：一种在硅衬底上制造单晶硅微电子元件并将其转移到玻璃衬底的方法。这通过利用用于制造体硅的电子电路和器件的部件的常规硅处理技术来实现，其中在常规处理之前制备具有外延层的体硅表面。将硅衬底接合到玻璃衬底上，并移除体硅，使组分在玻璃衬底表面上完好无损。随后的标准处理完成了器件和电路制造。本发明在需要透明或绝缘基材，特别是显示器制造的应用中是有用的。其他应用包括传感器，执行器，光电子，辐射硬电子和高温电子。

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