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1. 发明授权

US4569124A Method for forming thin conducting lines by ion implantation and preferential etching 失效
标题翻译：通过离子注入和优先蚀刻形成薄导线的方法
公开(公告)号：US4569124A
公开(公告)日：1986-02-11
申请号：US613114
申请日：1984-05-22
申请人： David B. Rensch , John Y. Chen
发明人： David B. Rensch , John Y. Chen
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/3213 , H01L21/3215 , H01L21/336 , H01L21/338 , H01L21/302 , H01L21/425
CPC分类号： H01L29/66863 , H01L21/32134 , H01L21/32136 , H01L21/32137 , H01L21/3215 , H01L21/32155 , H01L29/66575 , Y10S148/019 , Y10S148/083 , Y10S148/147 , Y10S438/942
摘要： A thin conducting line such as a gate pattern is defined on a semiconductor chip (10) by applying a narrow ion beam, suitably a focused-ion-beam (16) having a submicrometer thickness from a source (18) onto a thin layer (14) of an inorganic material such as silicon or aluminum overlying a layer (12) of refractory metal on a substrate (11). The ion beam is translated to form a gate pattern at a dose between about 0.1 to 50.times.10.sup.15 cm.sup.-2 and an energy from about 1 to 1000 KeV. Ions are implanted into the silicon and aluminum layers and into the underlying portions of the refractory metal layer and to render the exposed portions of the layers preferentially resistant to wet-etchant. The portions of layers which are not exposed nor protected by layers which are exposed, are preferentially removed to form a gate. Conventional MOSFET or MESFET processing to implant ions to form source and drain regions may then be performed.
摘要翻译：通过将窄离子束（适当地是具有亚微米厚度的聚焦离子束（16））从源（18）施加到薄层（10）上而限定在半导体芯片（10）上的薄导线 14）覆盖在基底（11）上的难熔金属层（12）上的无机材料，例如硅或铝。将离子束平移以在约0.1至50×10 15 cm -2之间的剂量和约1至1000KeV的能量下形成栅极图案。离子被植入到硅和铝层中并进入难熔金属层的下面部分，并且使得这些层的暴露部分优先抵抗湿蚀刻剂。优选地除去未暴露的层的不暴露的层的部分以形成栅极。然后可以执行用于注入离子以形成源区和漏区的常规MOSFET或MESFET处理。

2. 发明授权

US5528209A Monolithic microwave integrated circuit and method 失效
标题翻译：单片微波集成电路及方法
公开(公告)号：US5528209A
公开(公告)日：1996-06-18
申请号：US430067
申请日：1995-04-27
申请人： Perry A. Macdonald , Lawrence E. Larson , Michael G. Case , Mehran Matloubian , Mary Y. Chen , David B. Rensch
发明人： Perry A. Macdonald , Lawrence E. Larson , Michael G. Case , Mehran Matloubian , Mary Y. Chen , David B. Rensch
IPC分类号： H01L21/822 , H01L27/04 , H01L27/06 , H01L29/205 , H01P3/08 , H03F3/54 , H03H7/38 , H01P5/00
CPC分类号： H01L27/0605 , H01L2223/6627 , H01L2223/6644 , H01L2223/6683
摘要： A monolithic microwave integrated circuit is formed by positioning a distributed, transmission-line network over a microwave-device structure. The ground plane of the transmission-line network adjoins an interconnect system of the microwave-device structure and signal lines of the transmission-line network are adapted to communicate with the microwave-device structure through orifices of the ground plane. The invention facilitates the use of low-cost silicon-based transistors in monolithic microwave integrated circuits.
摘要翻译：通过在微波器件结构上定位分布式传输线网络来形成单片微波集成电路。传输线网络的接地平面与微波器件结构的互连系统相邻，并且传输线网络的信号线适于通过接地平面的孔与微波器件结构通信。本发明有助于在单片微波集成电路中使用低成本硅基晶体管。

3. 发明授权

US6028483A Universal fixture/package for spatial-power-combined amplifier 失效
标题翻译：用于空间功率组合放大器的通用夹具/封装
公开(公告)号：US6028483A
公开(公告)日：2000-02-22
申请号：US73705
申请日：1998-05-06
申请人： Jeffrey B. Shealy , David B. Rensch , Angelos Alexanian , Robert York
发明人： Jeffrey B. Shealy , David B. Rensch , Angelos Alexanian , Robert York
IPC分类号： H03F3/60
CPC分类号： H03F3/602 , H03F3/195 , H03F3/24
摘要： A combined test fixture and spatial-power-combined amplifier includes a base, a first waveguide mounting flange engaged to said base, a second waveguide mounting flange engaged to said base, a waveguide input fixed to said first flange, a waveguide output fixed to said second flange, an amplifier array disposed between said first flange and second flange, said array comprising a plurality of semiconductors for amplifying a signal, and a spacer for spacing apart said semiconductors. A plurality of amplifier cards constitute the array, with the cards being disposed in various arrangements which include a linearly stacked arrangement and radially stacked arrangement. The first and second waveguide mounting flanges are constructed to slide along the base to enable the amplifier array to be easily changed.
摘要翻译：组合的测试夹具和空间功率组合放大器包括基座，接合到所述基座的第一波导安装凸缘，接合到所述基座的第二波导安装凸缘，固定到所述第一凸缘的波导输入，固定到所述基座的波导输出第二凸缘，设置在所述第一凸缘和第二凸缘之间的放大器阵列，所述阵列包括用于放大信号的多个半导体，以及用于间隔开所述半导体的间隔件。多个放大器卡构成阵列，其中卡被布置成包括线性堆叠布置和径向堆叠布置的各种布置。第一和第二波导安装凸缘被构造成沿着底座滑动以使放大器阵列容易地改变。

4. 发明授权

US5404028A Electrical junction device with lightly doped buffer region to precisely locate a p-n junction 失效
标题翻译：具有轻掺杂缓冲区域的电连接器件，以精确定位p-n结
公开(公告)号：US5404028A
公开(公告)日：1995-04-04
申请号：US7705
申请日：1993-01-22
申请人： Robert A. Metzger , Madjid Hafizi , William E. Stanchina , David B. Rensch
发明人： Robert A. Metzger , Madjid Hafizi , William E. Stanchina , David B. Rensch
IPC分类号： H01L29/205 , H01L21/331 , H01L29/15 , H01L29/73 , H01L29/737 , H01L29/161 , H01L29/72
CPC分类号： H01L29/155 , H01L29/7371
摘要： An electrical junction is precisely located between a highly p doped semiconductor material and a more lightly n doped semiconductor material by providing a lightly p doped buffer region between the two materials, with a doping level on the order of the n doped material's. The buffer region is made wide enough to establish an electrical junction at approximately its interface with the n doped material, despite a diffusion of dopant from the p doped material. When applied to a heterojunction bipolar transistor (HBT), the transistor's base serves as the heavily p doped material and its emitter as the more lightly n doped material. The buffer region is preferably employed in conjunction with a graded superlattice, located between the buffer and emitter, which inhibits dopant diffusion from the base into the emitter. A p-n junction is formed within the superlattice, which functions on one side as an electrical extension of the emitter and on the other side as an electrical extension of the buffer, and establishes the electrical junction at the p-n junction location. The precise positioning of the electrical junction results in a known and repeatable emitter-base turn-on voltage.
摘要翻译：通过在两种材料之间提供轻掺杂的p型缓冲区，掺杂水平在n掺杂材料的数量级上，电接点精确地位于高掺杂p型半导体材料和更轻掺杂的半导体材料之间。尽管掺杂剂从p掺杂材料的扩散，缓冲区被制成足够宽以在大约与n掺杂材料的界面处建立电连接。当应用于异质结双极晶体管（HBT）时，晶体管的基极用作重p掺杂材料，其发射极是较轻掺杂的材料。缓冲区优选与位于缓冲区和发射极之间的渐变超晶格结合使用，其抑制掺杂剂从基极扩散到发射极中。在超晶格内形成p-n结，其在一侧作为发射极的电延伸，另一侧作为缓冲器的电延伸而起作用，并在p-n结位置建立电连接。电连接的精确定位导致已知且可重复的发射极基极导通电压。

5. 发明授权

US5629241A Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements, and method of fabricating the same 失效
标题翻译：具有分立倒装芯片安装元件的微波/毫米波电路结构及其制造方法
公开(公告)号：US5629241A
公开(公告)日：1997-05-13
申请号：US499800
申请日：1995-07-07
申请人： Mehran Matloubian , Perry A. Macdonald , David B. Rensch , Lawrence E. Larson
发明人： Mehran Matloubian , Perry A. Macdonald , David B. Rensch , Lawrence E. Larson
IPC分类号： H01L21/60 , H01L23/66 , H01P3/08 , H01Q23/00 , H05K1/02 , H05K3/34
CPC分类号： H01L25/162 , H01L23/66 , H01L24/81 , H01Q23/00 , H05K3/3452 , H01L2223/6677 , H01L2224/13111 , H01L2224/16 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/1305 , H01L2924/13064 , H01L2924/14 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H05K1/0237 , H05K2201/0175 , H05K2203/0315
摘要： A microwave/millimeter wave circuit structure supports discrete circuit elements by flip-chip mounting to an interconnection network on a low cost non-ceramic and non-semiconductor dielectric substrate, preferably Duroid. The necessary precise alignment of the circuit elements with contact pads on the substrate network required for the high operating frequencies is facilitated by oxidizing the interconnection network, but providing the contact pads from a non-oxidizable material to establish a preferential solder bump wetting for the pads. Alternately, the contact bumps on the flip-chips can be precisely positioned through corresponding openings in a passivation layer over the interconnection network. For thin circuit substrates that are too soft for successful flip-chip mounting, stiffening substrates are laminated to the circuit substrates. In a self-contained antenna application in which two of the circuit substrates are laminated together, with an antenna on one side and circuitry on the other side, a metallic ground plane between the substrates also serves a stiffening function.
摘要翻译：微波/毫米波电路结构通过倒装芯片安装到低成本非陶瓷和非半导体电介质基底（优选为Duroid）上的互连网络来支持分立电路元件。通过氧化互连网络来提供电路元件与高工作频率所需的基板网络上的接触焊盘的必要精确对准，但是提供来自不可氧化材料的接触焊盘以建立用于焊盘的优先焊料凸块润湿。或者，倒装芯片上的接触凸块可以通过互连网络上的钝化层中的相应开口精确定位。对于对于成功倒装芯片安装来说太软的薄电路基板，加固基板被层压到电路基板上。在其中两个电路基板层叠在一起的独立天线应用中，一侧的天线和另一侧的电路，在基板之间的金属接地平面也起增强作用。

6. 发明授权

US5532486A Heterojunction diode with low turn-on voltage 失效
标题翻译：具有低导通电压的异质结二极管
公开(公告)号：US5532486A
公开(公告)日：1996-07-02
申请号：US387507
申请日：1995-02-13
申请人： William E. Stanchina , Robert A. Metzger , David B. Rensch
发明人： William E. Stanchina , Robert A. Metzger , David B. Rensch
IPC分类号： H01L29/205 , H01L29/861 , H01L31/0328
CPC分类号： H01L29/205 , H01L29/861 , Y10S257/916
摘要： A high speed diode with a low forward-bias turn-on voltage is formed by a heterojunction between a layer of doped semiconductor material that has a narrow bandgap energy of not more than about 0.4 eV, and a layer of oppositely doped semiconductor material that has a substantially wider bandgap energy. The device operates with a lower turn-on voltage than has previously been attainable, despite lattice mismatches between the two materials that can produce strain and substantial lattice dislocations in the low bandgap material. The two materials are selected so that the valence and conduction band edge discontinuities at the heterojunction enable a forward carrier flow but block a reverse carrier flow across the junction under forward-bias conditions. Preferred material systems are InAs for the narrow bandgap material, InGaAs for the wider bandgap material and InP for the substrate, or AlSb for the wider bandgap material and GaSb for the substrate. A compositional grading can be provided at the heterojunction to reduce energy band spikes, and a region of low dopant concentration is included in the wider bandgap material to increase the diode's reverse-bias breakdown voltage.
摘要翻译：具有低正向偏置导通电压的高速二极管通过具有窄度不大于约0.4eV的窄带隙能量的掺杂半导体材料层与具有不超过约0.4eV的相反掺杂半导体材料的层之间的异质结形成，一个实质上更宽的带隙能量。尽管在低带隙材料中可能产生应变和大量晶格位错的两种材料之间晶格不匹配，器件以比以前可获得的更低的导通电压工作。选择两种材料使得异质结的价带和导带边缘不连续能够实现正向载流，但在正向偏置条件下阻塞跨接点的反向载流。优选的材料系统是用于窄带隙材料的InAs，用于更宽带隙材料的InGaAs和用于衬底的InP，或用于更宽带隙材料的AlSb和用于衬底的GaSb。可以在异质结处提供组成分级以减少能带尖峰，并且较宽带隙材料中包括低掺杂剂浓度的区域以增加二极管的反偏压击穿电压。

7. 发明授权

US5757074A Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements 失效
标题翻译：微波/毫米波电路结构，具有分立的倒装芯片安装元件
公开(公告)号：US5757074A
公开(公告)日：1998-05-26
申请号：US681688
申请日：1996-07-29
申请人： Mehran Matloubian , Perry A. Macdonald , David B. Rensch , Lawrence E. Larson
发明人： Mehran Matloubian , Perry A. Macdonald , David B. Rensch , Lawrence E. Larson
IPC分类号： H01L21/60 , H01L23/66 , H01P3/08 , H01Q23/00 , H05K1/02 , H05K3/34 , H01L23/14
CPC分类号： H01L25/162 , H01L23/66 , H01L24/81 , H01Q23/00 , H05K3/3452 , H01L2223/6677 , H01L2224/13111 , H01L2224/16 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/1305 , H01L2924/13064 , H01L2924/14 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H05K1/0237 , H05K2201/0175 , H05K2203/0315
摘要： A microwave/millimeter wave circuit structure supports discrete circuit elements by flip-chip mounting to an interconnection network on a low cost non-ceramic and non-semiconductor dielectric substrate, preferably Duroid. The necessary precise alignment of the circuit elements with contact pads on the substrate network required for the high operating frequencies is facilitated by oxidizing the interconnection network, but providing the contact pads from a non-oxidizable material to establish a preferential solder bump wetting for the pads. Alternately, the contact bumps on the flip-chips can be precisely positioned through corresponding openings in a passivation layer over the interconnection network. For thin circuit substrates that are too soft for successful flip-chip mounting, stiffening substrates are laminated to the circuit substrates. In a self-contained antenna application in which two of the circuit substrates are laminated together, with an antenna on one side and circuitry on the other side, a metallic ground plane between the substrates also serves a stiffening function.
摘要翻译：微波/毫米波电路结构通过倒装芯片安装到低成本非陶瓷和非半导体电介质基底（优选为Duroid）上的互连网络来支持分立电路元件。通过氧化互连网络来提供电路元件与高工作频率所需的基板网络上的接触焊盘的必要精确对准，但是提供来自不可氧化材料的接触焊盘以建立用于焊盘的优先焊料凸块润湿。或者，倒装芯片上的接触凸块可以通过互连网络上的钝化层中的相应开口精确定位。对于对于成功倒装芯片安装来说太软的薄电路基板，加固基板被层压到电路基板上。在其中两个电路基板层叠在一起的独立天线应用中，一侧的天线和另一侧的电路，在基板之间的金属接地平面也起增强作用。

8. 发明授权

US5114910A Passivation of thin film oxide superconductors 失效
标题翻译：薄膜氧化物超导体的钝化
公开(公告)号：US5114910A
公开(公告)日：1992-05-19
申请号：US608120
申请日：1990-11-01
申请人： Jack Y. Josefowicz , David B. Rensch , Kai-Wei Nieh
发明人： Jack Y. Josefowicz , David B. Rensch , Kai-Wei Nieh
IPC分类号： C01G1/00 , C01G3/00 , C04B41/89 , C30B29/22 , H01B12/06 , H01B13/00 , H01L39/24
CPC分类号： H01L39/247 , Y10S428/93 , Y10S505/701 , Y10S505/702 , Y10S505/703 , Y10S505/704 , Y10T428/239 , Y10T428/31721
摘要： An oxide superconductor having a high critical temperature is provided with a passivation coating comprising a first layer of a Group II oxide, such as magnesium oxide, and a second layer of a polymer, such as polyimide. The Group II oxide is formed under conditions to be substantially amorphous. After depositing the Group II layer, the encapsulated superconductor is heated to an elevated temperature for a period of time in an oxidizing atmosphere. This restores the high critical temperature to its original value. The polymer is then coated on top of the Group II oxide and cured. The passivation coating is resistant to strong acids, strong bases, and water, is robust, hard, and resilient against scratching.

9. 发明授权

US06274922B1 Fabrication of high power semiconductor device with a heat sink and integration with planar microstrip circuitry 有权
标题翻译：具有散热器并与平面微带电路集成的大功率半导体器件的制造
公开(公告)号：US06274922B1
公开(公告)日：2001-08-14
申请号：US09334165
申请日：1999-06-15
申请人： Debabani Choudhury , James A. Foschaar , Phillip H. Lawyer , David B. Rensch
发明人： Debabani Choudhury , James A. Foschaar , Phillip H. Lawyer , David B. Rensch
IPC分类号： H01L21302
CPC分类号： H01L23/36 , H01L21/4871 , H01L2224/48091 , H01L2924/1305 , H01L2924/00014 , H01L2924/00
摘要： A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.
摘要翻译：在功率半导体器件的背面上制造散热器的低成本高度集成的方法保持器件性能，改善热传递，并且实现可靠的平面连接，而不必将晶片或封装成分立的器件 - 散热器组件。在晶片和前侧功率器件之间形成蚀刻停止层，以在背面处理期间保护它们，并降低器件与其散热器之间的接触电阻。散热器通过使薄片变薄，图案化，然后以晶片的方式进行电镀而形成，使得可以在没有切割的情况下释放器件。散热器优选地是过大的，使得真空工具可以从上面抓住散热器而不会损坏设备，然后将散热器压缩到平面微带电路组件上，该平面微带电路组件被设计和封装以便于容易地更换故障设备。

10. 发明授权

US6048777A Fabrication of high power semiconductor devices with respective heat sinks for integration with planar microstrip circuitry 失效
标题翻译：制造具有相应散热器的大功率半导体器件，用于与平面微带电路集成
公开(公告)号：US6048777A
公开(公告)日：2000-04-11
申请号：US992882
申请日：1997-12-18
申请人： Debabani Choudhury , James A. Foschaar , Phillip H. Lawyer , David B. Rensch
发明人： Debabani Choudhury , James A. Foschaar , Phillip H. Lawyer , David B. Rensch
IPC分类号： H01L21/48 , H01L23/36 , H01L21/265
CPC分类号： H01L23/36 , H01L21/4871 , H01L2224/48091 , H01L2924/1305
摘要： A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.
摘要翻译：在功率半导体器件的背面上制造散热器的低成本高度集成的方法保持器件性能，改善热传递，并且实现可靠的平面连接，而不必将晶片或封装成分立的器件 - 散热器组件。在晶片和前侧功率器件之间形成蚀刻停止层，以在背面处理期间保护它们，并降低器件与其散热器之间的接触电阻。散热器通过使薄片化，图形化，然后以晶片的方式镀覆而形成，使得可以在不切割的情况下释放器件。散热器优选地是过大的，使得真空工具可以从上面抓住散热器而不会损坏设备，然后将散热器压缩到平面微带电路组件上，该平面微带电路组件被设计和封装以便于容易地更换故障设备。

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