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1. 发明授权

US07629914B2 Counter circuit, AD conversion method, AD converter, semiconductor device for detecting distribution of physical quantities, and electronic apparatus 有权
标题翻译：计数器电路，AD转换方法，AD转换器，用于检测物理量分布的半导体器件和电子设备
公开(公告)号：US07629914B2
公开(公告)日：2009-12-08
申请号：US12329682
申请日：2008-12-08
申请人： Yoshinori Muramatsu , Noriyuki Fukushima , Yoshikazu Nitta , Yukihiro Yasui
发明人： Yoshinori Muramatsu , Noriyuki Fukushima , Yoshikazu Nitta , Yukihiro Yasui
IPC分类号： H03M1/34
CPC分类号： H03K23/62 , H03K23/56 , H03M1/1023 , H03M1/123 , H03M1/1295 , H03M1/56 , H04N5/335
摘要： A solid-state image pick up device including a pixel array unit having unit pixels arranged in a matrix pattern. Each unit pixel includes a photoelectric converter. Additionally, the solid-state image pick up device has column signal lines that correspond to the respective columns of the matrix pattern, a row scanning means for selectively controlling each unit pixel, and an analog-digital converting unit for converting analog signals output from the unit pixels in a row selectively controlled by the row scanning means. The analog-digital converting unit further includes an asynchronous counter which performs counting in two modes and the asynchronous counter includes a counter processor configured so that when switching between the count modes occurs, a running count value is broken and there is an interval between the count modes and when a mode begins the running count value is reset to the value before the running count value was broken.
摘要翻译：一种固态图像拾取装置，包括具有以矩阵图案排列的单位像素的像素阵列单元。每个单位像素包括光电转换器。此外，固态图像拾取装置具有与矩阵图案的各列相对应的列信号线，用于选择性地控制每个单位像素的行扫描装置，以及用于转换从单元像素输出的模拟信号的模拟数字转换单元由行扫描装置选择性地控制的行中的单位像素。模拟数字转换单元还包括以两种模式执行计数的异步计数器，并且异步计数器包括配置为当在计数模式之间切换时发生计数模式的计数器处理器，运行计数值被破坏并且计数之间存在间隔模式，当模式开始时，运行计数值将重置为运行计数值中断之前的值。

2. 发明授权

US07487200B1 Method and apparatus for performing priority encoding in a segmented classification system 有权
标题翻译：在分段分类系统中执行优先编码的方法和装置
公开(公告)号：US07487200B1
公开(公告)日：2009-02-03
申请号：US09729871
申请日：2000-12-05
申请人： Varadarajan Srinivasan
发明人： Varadarajan Srinivasan
IPC分类号： G06F15/16
CPC分类号： G11C8/04 , G11C15/04 , H03K23/56
摘要： A digital signal processor. The digital signal processor includes a first data classification block. The first data classification block outputs a first block priority number associated with a first data stored in the first data classification block that matches a search key. The digital signal processor includes a second data classification block. The second data classification block outputs a second priority number associated with a second data stored in the second data classification block that matches the search key. The digital signal processor includes a device index processor. The device index processor selects a most significant block priority number from the first block priority number and the second block priority number.
摘要翻译：数字信号处理器。数字信号处理器包括第一数据分类块。第一数据分类块输出与存储在与搜索关键字匹配的第一数据分类块中的第一数据相关联的第一块优先级编号。数字信号处理器包括第二数据分类块。第二数据分类块输出与存储在与搜索关键字匹配的第二数据分类块中的第二数据相关联的第二优先权编号。数字信号处理器包括设备索引处理器。设备索引处理器从第一块优先权号码和第二块优先权号码中选择最高有效的块优先权号码。

3. 发明授权

US07110408B1 Method and apparatus for selecting a most signficant priority number for a device using a partitioned priority index table 有权
标题翻译：使用分区优先级索引表为设备选择最重要的优先级编号的方法和装置
公开(公告)号：US07110408B1
公开(公告)日：2006-09-19
申请号：US09815921
申请日：2001-03-24
申请人： Bindiganavale S. Nataraj
发明人： Bindiganavale S. Nataraj
IPC分类号： H04L12/28 , G06F12/00 , G06F13/00
CPC分类号： H03K3/356139 , G11C8/04 , G11C15/04 , H03K23/56
摘要： A digital signal processor. The digital signal processor includes a content addressable memory (CAM) array for storing entries. The digital signal processor includes a partitioned priority index table having a plurality of rows and columns of priority blocks. Each row of the plurality of rows of priority blocks is capable of storing a priority number associated with an entry in the CAM array. Each column of the plurality of columns of priority blocks has compare logic coupled to each of the priority blocks in its respective column. The digital signal processor includes an encoder coupled to the partitioned priority index table.
摘要翻译：数字信号处理器。数字信号处理器包括用于存储条目的内容可寻址存储器（CAM）阵列。数字信号处理器包括具有多个优先权块的行和列的分区优先级索引表。多行优先级块的每行能够存储与CAM阵列中的条目相关联的优先权号码。多列优先级块中的每一列具有耦合到其相应列中每个优先级块的比较逻辑。数字信号处理器包括耦合到分区优先级索引表的编码器。

4. 发明授权

US06934795B2 Content addressable memory with programmable word width and programmable priority 有权
标题翻译：内容可寻址存储器，具有可编程字宽和可编程优先级
公开(公告)号：US06934795B2
公开(公告)日：2005-08-23
申请号：US10000122
申请日：2001-10-31
申请人： Bindiganavale S. Nataraj , Nilesh A. Gharia , Rupesh R. Roy , Jose P. Pereira , Varadarajan Srinivasan , Sandeep Khanna , Hok F. Wong
发明人： Bindiganavale S. Nataraj , Nilesh A. Gharia , Rupesh R. Roy , Jose P. Pereira , Varadarajan Srinivasan , Sandeep Khanna , Hok F. Wong
IPC分类号： G06F12/00 , G06F17/30 , G11C8/04 , G11C15/00 , G11C15/04 , H03K3/356 , H03K23/56 , G06F13/00
CPC分类号： G11C15/04 , G06F17/30982 , G11C8/04 , G11C15/00 , H03K3/356139 , H03K23/56
摘要： A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.
摘要翻译：包括CAM阵列和优先级索引表的内容可寻址存储器（CAM）装置。 CAM阵列具有多行CAM单元，每行包括多个行段，并且适于存储跨越可选数量的行段的数据字。优先权索引表耦合到多个CAM单元行，并且适于存储多个优先级数，每个优先级数表示存储在CAM阵列中的相应数据字的优先级。

5. 发明授权

US6157209A Loadable up-down counter with asynchronous reset 有权
标题翻译：可异步复位的可加载上拉计数器
公开(公告)号：US6157209A
公开(公告)日：2000-12-05
申请号：US216277
申请日：1998-12-18
申请人： Edward S. McGettigan
发明人： Edward S. McGettigan
IPC分类号： G06F7/50 , G06F7/505 , H03K19/173 , H03K23/56 , H03K23/66 , G06F7/38
CPC分类号： G06F7/5055 , H03K19/17728 , H03K23/56 , H03K23/665 , H03K19/1737
摘要： In an FPGA having four-input lookup tables (LUTs) with parallel two-input AND gates receiving two of the four LUT input signals, associated registers, and a carry chain receiving one input signal from the AND gate output, a loadable up-down counter is formed by connecting the register output to one of the terminals serving as both a LUT input terminal and an AND gate input terminal. A load control signal is connected to another input terminal common to the LUT and the AND gate. Thus the AND gate disables the carry chain during loading of the counter and applies the count value to the carry chain during counting.
摘要翻译：在具有并行双输入与门的四输入查找表（LUT）的FPGA中，接收四个LUT输入信号中的两个，相关联的寄存器和从AND门输出接收一个输入信号的进位链，可加载的上下通过将寄存器输出连接到用作LUT输入端子和与门输入端子的端子之一来形成计数器。负载控制信号连接到LUT和AND门公共的另一个输入端。因此，与门在加载计数器期间禁用进位链，并在计数期间将计数值应用于进位链。

6. 发明授权

US4637038A High speed counter 失效
标题翻译：高速计数器
公开(公告)号：US4637038A
公开(公告)日：1987-01-13
申请号：US728964
申请日：1985-04-30
申请人： David H. Boyle
发明人： David H. Boyle
IPC分类号： H03K23/00 , H03K23/50 , H03K23/56 , H03K23/60 , H03K23/62
CPC分类号： H03K23/56 , H03K23/50
摘要： An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subsequent value decoder which has the function of determining the effect of lower order carry bits on higher order stages with a minimum of signal delay. The decoder includes the feature of using natural threshold FET devices in a transfer gate configuration to perform logical AND functions so as to minimize gate delays in decoding a carry condition for higher order stages. A selective up-counting or down-counting function is also disclosed.
摘要翻译：公开了具有M个顺序上升二进制值级的M位二进制计数器，第一级是最低有效位。根据本发明，最低有效位级之上的每个级具有随后的值解码器，其具有以最小的信号延迟来确定较低阶进位位对高阶级的影响的功能。解码器包括在传输门配置中使用自然阈值FET器件来执行逻辑与功能的特征，以便最小化用于解码高阶级的进位条件的门延迟。还公开了选择性递增计数或递减计数功能。

7. 发明授权

US4611337A Minimal logic synchronous up/down counter implementations for CMOS 失效
标题翻译： CMOS的最小逻辑同步上/下计数器实现
公开(公告)号：US4611337A
公开(公告)日：1986-09-09
申请号：US527470
申请日：1983-08-29
申请人： Michael W. Evans
发明人： Michael W. Evans
IPC分类号： H03K23/00 , H03K23/56
CPC分类号： H03K23/56
摘要： A binary up/down counter stage particularly suitable for CMOS implementation. The counter stage includes an exclusive OR gate having a first input for receiving a toggle signal, a flip-flop having a data input coupled to the output of the exclusive OR gate and Q and Q outputs, the Q output of which provides the stage output and a feedback to the second input of the exclusive OR gate, and a multiplexer having first and second inputs coupled to the Q and Q of the flip-flop respectively, the output of the multiplexer being logically ANDED with a toggle-in signal to provide a toggle-out signal for a further counter stage in cascade.
摘要翻译：二进制上/下计数器级特别适用于CMOS实现。计数器级包括具有用于接收触发信号的第一输入的异或门，具有耦合到异或门的输出的数据输入的触发器和Q和＆amp;上升＆Q输出，其Q输出提供阶段输出和对异或门的第二输入的反馈，以及多路复用器，其具有分别耦合到触发器的Q和＆amp; Upbar＆Q的第一和第二输入，多路复用器的输出与触发输入信号以级联地提供用于另外的计数器级的切换信号。

8. 发明授权

US3155836A Electronic counter circuit selectively responsive to input pulses for forward or reverse 失效
标题翻译：电子计数器电路选择性地响应用于正向或反向的输入脉冲
公开(公告)号：US3155836A
公开(公告)日：1964-11-03
申请号：US82987059
申请日：1959-07-27
申请人： TEXTRON ELECTRONICS INC
发明人： HEMPEL ROY A
IPC分类号： H03K23/50 , H03K23/56
CPC分类号： H03K23/56 , H03K23/505

9. 发明授权

US3145292A Forward-backward counter 失效
标题翻译：前后计数器
公开(公告)号：US3145292A
公开(公告)日：1964-08-18
申请号：US10386461
申请日：1961-04-18
申请人： SPERRY RAND CORP
发明人： SCHWANINGER JOSEPH W
IPC分类号： H03K23/56
CPC分类号： H03K23/56

10. 发明授权

US09870316B2 Bidirectional counter in a flash memory 有权
公开(公告)号：US09870316B2
公开(公告)日：2018-01-16
申请号：US15243359
申请日：2016-08-22
申请人： Proton World International N.V.
发明人： Ronny Van Keer , Guillaume Docquier
IPC分类号： G06F12/00 , G06F13/00 , G06F12/02 , G06F9/30 , G11C16/10 , H03K21/40 , H03K23/56
CPC分类号： G06F12/0246 , G06F9/3001 , G06F2212/7207 , G11C16/105 , H03K21/403 , H03K23/56
摘要： A method of storing a counter in at least two non-volatile memory pages, including: a step of initializing a page with an initial value and then, on each update of the counter value, a step of storing an update value and an opcode associated with this value, selected from a set of opcodes, the current value of the counter being given by application of the successive update operations to the initial value of the page.

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