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1. 发明授权

US5430781A Variable pulse width generator circuit 失效
标题翻译：可变脉宽发生电路
公开(公告)号：US5430781A
公开(公告)日：1995-07-04
申请号：US128968
申请日：1993-09-30
申请人： Takashi Miyake , Nobusuke Abe
发明人： Takashi Miyake , Nobusuke Abe
IPC分类号： H03K23/60 , G06F1/025 , G06F7/62 , H03K5/05 , H03K21/00 , H03K23/66 , H03K21/08 , G06M3/02
CPC分类号： G06F1/025 , G06F7/62 , H03K5/05
摘要： A comparator is provided in the counter circuit to compare the counted value of clocks by a counter with the value of a register in which a target changing value of a comparison register which sets a value to be compared with the counted value of the counter is set. The value of the register is set in the comparison register when the counted value of the counter does not reach the set value of the register, whereas the value of the register is not set in the comparison register if the counted value does not reach the set value of the register, but the value of the comparison register is turned changeable at the desired timing while the counted value of the counter is being compared with the set value of the comparison register.
摘要翻译：在计数器电路中提供比较器，以将计数器的计数值与其中设定要与计数器的计数值进行比较的值的比较寄存器的目标变化值设置的寄存器的值进行比较。当计数器的计数值未达到寄存器的设定值时，寄存器的值被设置在比较寄存器中，而如果计数值未达到设定值，则寄存器的值未设置在比较寄存器中值，但是比较寄存器的值在期望的定时可变，而计数器的计数值与比较寄存器的设定值进行比较。

2. 发明授权

US09748959B2 Circuits, apparatuses, and methods for frequency division 有权
公开(公告)号：US09748959B2
公开(公告)日：2017-08-29
申请号：US13418166
申请日：2012-03-12
申请人： Tyler J. Gomm
发明人： Tyler J. Gomm
IPC分类号： H03K21/38 , H03K23/44 , H03K23/60 , H03B19/06
CPC分类号： H03K21/38
摘要： Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.

3. 发明授权

US4637038A High speed counter 失效
标题翻译：高速计数器
公开(公告)号：US4637038A
公开(公告)日：1987-01-13
申请号：US728964
申请日：1985-04-30
申请人： David H. Boyle
发明人： David H. Boyle
IPC分类号： H03K23/00 , H03K23/50 , H03K23/56 , H03K23/60 , H03K23/62
CPC分类号： H03K23/56 , H03K23/50
摘要： An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subsequent value decoder which has the function of determining the effect of lower order carry bits on higher order stages with a minimum of signal delay. The decoder includes the feature of using natural threshold FET devices in a transfer gate configuration to perform logical AND functions so as to minimize gate delays in decoding a carry condition for higher order stages. A selective up-counting or down-counting function is also disclosed.
摘要翻译：公开了具有M个顺序上升二进制值级的M位二进制计数器，第一级是最低有效位。根据本发明，最低有效位级之上的每个级具有随后的值解码器，其具有以最小的信号延迟来确定较低阶进位位对高阶级的影响的功能。解码器包括在传输门配置中使用自然阈值FET器件来执行逻辑与功能的特征，以便最小化用于解码高阶级的进位条件的门延迟。还公开了选择性递增计数或递减计数功能。

4. 发明申请

US20230059517A1 CLOCK AND PHASE ALIGNMENT BETWEEN PHYSICAL LAYERS AND CONTROLLER 有权
公开(公告)号：US20230059517A1
公开(公告)日：2023-02-23
申请号：US17405854
申请日：2021-08-18
申请人： XILINX, INC.
发明人： Sarosh I. AZAD , Benson CHAU , Tomai KNOPP
IPC分类号： H03K5/02 , H03K23/60 , H03K19/173 , H03K19/20
摘要： An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

5. 发明授权

US4680482A Inverter for use in binary counter 失效
标题翻译：逆变器用于二进制计数器
公开(公告)号：US4680482A
公开(公告)日：1987-07-14
申请号：US886156
申请日：1986-07-16
申请人： Takashi Obara
发明人： Takashi Obara
IPC分类号： H03K23/00 , G11C11/406 , H03K3/037 , H03K3/356 , H03K23/52 , H03K23/60
CPC分类号： H03K3/35606 , H03K3/356017
摘要： An inverter for use in a binary counter comprises a flip-flop having first and second input/output nodes respectively applied with input signals of opposite polarities, a first field effect transistor having a source-drain path connected between the first input/output node and a third node and a gate connected to receive a control clock signal, and a capacitor connected to the third node so as to hold the potential on the first input/output node when the first transistor is turned on. Further, there is provided a switch circuit connected between a supply voltage and a ground and having a first input connected to the third node, a second input connected to receive an inversion control signal, and an output connected to the first input/output node. This switch circuit is responsive to the inversion control signal so as to bring its output to a voltage condition opposite to that held in the capacitor.
摘要翻译：用于二进制计数器的反相器包括具有分别施加相反极性的输入信号的第一和第二输入/输出节点的触发器，具有连接在第一输入/输出节点与第一输入/输出节点之间的源极 - 漏极路径的第一场效应晶体管，连接以接收控制时钟信号的第三节点和栅极，以及连接到第三节点的电容器，以便当第一晶体管导通时将电位保持在第一输入/输出节点上。此外，提供了连接在电源电压和地之间并具有连接到第三节点的第一输入端的开关电路，连接以接收反相控制信号的第二输入端和连接到第一输入/输出节点的输出端。该开关电路响应于反相控制信号，使其输出达到与保持在电容器中的电压相反的电压条件。

6. 发明授权

US3706043A Synchronous parallel counter with common steering of clock pulses to binary stages 失效
标题翻译：同步时序脉冲同步转换的同步并行计数器
公开(公告)号：US3706043A
公开(公告)日：1972-12-12
申请号：US3706043D
申请日：1971-09-30
申请人： MOTOROLA INC
发明人： REINERT JOHN R
IPC分类号： H03K21/02 , H03K21/00 , H03K23/58 , H03K23/60 , H03K21/16
CPC分类号： H03K21/00
摘要： PARALLEL COUNTER CONSTRUCTED AS AN INTEGRATED CIRCUIT WITH A PLURALITY OF PAIRS OF NAND GATES FORMING BINARY STAGES, AND A STEERING CIRCUIT INCLUDING INPUT NAND GATES ASSOCIATED WITH THE BINARY STAGES. THE STEERING CIRCUIT INCLUDES COUPLING FROM THE OUTPUTS OF THE BINARY STAGES TO THE INPUTS OF THE HIGHER ORDER INPUT NAND GATE, AND ALSO COUPLINGS FROM THE OUTPUTS OF THE INPUT NAND GATES TO RESET INPUTS OF THE LOWER ORDER BINARY STAGES. THE CLOCK PULSES MAY OR MAY NOT BE PERIODIC AND MAY HAVE DIFFERENT PULSE DURATIONS, AND AN INPUT CIRCUIT COUPLED TO ALL OF THE INPUT NAND GATES DISABLES THE SAME AT A PREDETERMINED TIME AFTER THE BEGINNING OF EACH CLOCK PULSE. A RESET GATE IS COUPLED TO THE RESET INPUT OF THE HIGHEST ORDER BINARY STAGE TO RESET THE COUNTER AT THE DESIRED COUNT.

7. 发明授权

US10164642B2 Circuits, apparatuses, and methods for frequency division 有权
公开(公告)号：US10164642B2
公开(公告)日：2018-12-25
申请号：US15644401
申请日：2017-07-07
申请人： MICRON TECHNOLOGY, INC.
发明人： Tyler J. Gomm
IPC分类号： H03K21/38 , H03K23/44 , H03K23/60 , H03B19/06
摘要： Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.

8. 发明授权

US3829712A Frequency divider circuit incorporating presetting means 失效
标题翻译：具有预先设定的频率分路电路
公开(公告)号：US3829712A
公开(公告)日：1974-08-13
申请号：US21595971
申请日：1971-12-29
申请人： SUWA SEIKOSHA KK
发明人： HAMA T
IPC分类号： G04G3/02 , G04G5/02 , H03K21/38 , H03K23/60 , H03K23/08
CPC分类号： G04G3/022 , G04G3/02 , G04G5/02 , H03K21/38 , H03K23/60
摘要： A frequency divider circuit having master-slave type flip-flop binary circuits formed from complementary insulated gate field effect transistors. Presetting means incorporated in one of the master or slave flip-flop circuits, the clock signal for the flip-flop circuit not having said presetting means is adapted so that said flip-flop circuit is subordinate to the flip-flop circuit incorporating the presetting means during the presetting operation.

9. 发明授权

US3500064A Field effect transistor digital forward and reverse counting circuit 失效
标题翻译：场效应晶体管数字转向和反向计数电路
公开(公告)号：US3500064A
公开(公告)日：1970-03-10
申请号：US3500064D
申请日：1966-04-22
申请人： US NAVY
发明人： WONG HAROLD Y
IPC分类号： H03K3/356 , H03K23/60 , H03K23/62 , H03K21/00
CPC分类号： H03K3/356 , H03K23/60 , H03K23/62

10. 发明授权

US11581881B1 Clock and phase alignment between physical layers and controller 有权
公开(公告)号：US11581881B1
公开(公告)日：2023-02-14
申请号：US17405854
申请日：2021-08-18
申请人： XILINX, INC.
发明人： Sarosh I. Azad , Benson Chau , Tomai Knopp
IPC分类号： H03K5/02 , H03K23/60 , H03K19/20 , H03K19/173 , H03K5/00
摘要： An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

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