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1. 发明申请

US20190036539A1 RADIO FREQUENCY FLASH ADC CIRCUITS 审中-公开
公开(公告)号：US20190036539A1
公开(公告)日：2019-01-31
申请号：US16147269
申请日：2018-09-28
申请人： Maxlinear Asia Singapore PTE LTD
发明人： William Michael LYE , Anthony Eugene ZORTEA , Jatinder CHANA
IPC分类号： H03M1/12 , H03M1/20 , H03K5/24 , H03M1/10 , H03M1/36
CPC分类号： H03M1/1245 , H03K5/249 , H03M1/1023 , H03M1/204 , H03M1/365
摘要： A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.

2. 发明授权

US10057531B2 Solid-state image pickup device and method for driving the same in solid-state imaging pickup device and method for driving the same in a number of modes 有权
公开(公告)号：US10057531B2
公开(公告)日：2018-08-21
申请号：US15893425
申请日：2018-02-09
申请人： Sony Corporation
发明人： Yoshikazu Nitta , Noriyuki Fukushima , Yoshinori Muramatsu , Yukihiko Yasui
IPC分类号： H04N5/378 , H04N5/374 , H04N5/347 , H04N3/14 , H04N5/3745 , H04N5/225 , H04M1/10 , H03M1/10 , H03M1/56
CPC分类号： H04N5/378 , H03M1/1023 , H03M1/56 , H04N3/1562 , H04N5/2253 , H04N5/347 , H04N5/3742 , H04N5/37455
摘要： A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.

3. 发明授权

US10056914B2 Frequency-domain ADC flash calibration 有权
公开(公告)号：US10056914B2
公开(公告)日：2018-08-21
申请号：US15282586
申请日：2016-09-30
申请人： ANALOG DEVICES GLOBAL
发明人： Zhao Li , Hajime Shibata , Trevor Clifford Caldwell , Richard E. Schreier , Victor Kozlov , David Nelson Alldred , Prawal Man Shrestha
IPC分类号： H03M1/10 , H03M1/36 , H03M3/00
CPC分类号： H03M1/1023 , H03M1/1004 , H03M1/1038 , H03M1/1085 , H03M1/361 , H03M3/378 , H03M3/384
摘要： A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

4. 发明申请

US20180006564A1 AUTO CALIBRATION METHOD USED IN CONSTANT ON-TIME SWITCHING CONVERTER 有权
公开(公告)号：US20180006564A1
公开(公告)日：2018-01-04
申请号：US15633688
申请日：2017-06-26
申请人： Chengdu Monolithic Power Systems Co., Ltd.
发明人： Changxian Zhong
IPC分类号： H02M3/158 , H03M1/80 , H03M1/10 , H03K17/16 , H04W76/04 , H03M1/52 , H02M1/00
CPC分类号： H02M3/158 , H02M1/36 , H02M2001/0025 , H02M2001/0032 , H03K3/017 , H03K17/16 , H03M1/1014 , H03M1/1023 , H03M1/52 , H03M1/804 , H04W76/23
摘要： An auto calibration method used in switching converters with constant on-time control. The auto calibration method includes: generating a periodical clock signal with a predetermined duty cycle; providing a first voltage and a second voltage to an on-time control circuit to generate an on-time control signal based on the first and second voltage; providing the clock signal and on-time control signal to a logic circuit to generate a switch control signal based on the clock signal and on-time control signal; comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.

5. 发明授权

US09806733B1 Hybrid analog-to-digital converter 有权
公开(公告)号：US09806733B1
公开(公告)日：2017-10-31
申请号：US15339200
申请日：2016-10-31
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Martin Kinyua
IPC分类号： H03M1/06 , H03M1/12 , G04F10/00 , H03M1/10 , H04N5/378
CPC分类号： H03M1/124 , G04F10/005 , H03M1/1023 , H03M1/164 , H03M1/502 , H04N5/378
摘要： An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal.

6. 发明申请

US20170194979A1 ANALOG TO DIGITAL CONVERSION CIRCUIT 有权
公开(公告)号：US20170194979A1
公开(公告)日：2017-07-06
申请号：US15371101
申请日：2016-12-06
申请人： Renesas Electronics Corporation
发明人： Yoshihiro FUNATO , Yasuo MORIMOTO , Kazuaki KUROOKA
IPC分类号： H03M1/06 , H03M1/12 , H03M1/10
CPC分类号： H03M1/0617 , H03M1/1023 , H03M1/1038 , H03M1/1057 , H03M1/12 , H03M1/145
摘要： During a period of calibration of the ADC, the effect of unexpected external noise can be excluded.Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.

7. 发明申请

US20170179971A1 FREQUENCY-DOMAIN ADC FLASH CALIBRATION 审中-公开
公开(公告)号：US20170179971A1
公开(公告)日：2017-06-22
申请号：US15282586
申请日：2016-09-30
申请人： ANALOG DEVICES GLOBAL
发明人： ZHAO LI , HAJIME SHIBATA , TREVOR CLIFFORD CALDWELL , RICHARD E. SCHREIER , VICTOR KOZLOV , DAVID NELSON ALLDRED , PRAWAL MAN SHRESTHA
IPC分类号： H03M1/10 , H03M3/00 , H03M1/36
CPC分类号： H03M1/1023 , H03M1/1004 , H03M1/1038 , H03M1/1085 , H03M1/361 , H03M3/378 , H03M3/384
摘要： A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

8. 发明申请

US20170134034A1 SYSTEMS AND METHODS FOR COMPARATOR CALIBRATION 有权
公开(公告)号：US20170134034A1
公开(公告)日：2017-05-11
申请号：US15375029
申请日：2016-12-09
申请人： INPHI CORPORATION
发明人： Mohammad RANJBAR , Jorge PERNILLO
IPC分类号： H03M1/10 , H03M1/38 , H03M1/68
CPC分类号： H03M1/1028 , H03K5/082 , H03M1/1023 , H03M1/36 , H03M1/38 , H03M1/662 , H03M1/68
摘要： The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

9. 发明授权

US09621176B2 Offset correction for sense amplifier 有权
公开(公告)号：US09621176B2
公开(公告)日：2017-04-11
申请号：US15277076
申请日：2016-09-27
申请人： INPHI CORPORATION
发明人： Parmanand Mishra , Simon Forey
IPC分类号： H03M1/10 , H04L25/03 , H03M1/66
CPC分类号： H03M1/1023 , H03M1/66 , H04L25/03057 , H04L25/03878
摘要： The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well.

10. 发明授权

US09559711B2 A/D converter including multiple sub-A/D converters 有权
标题翻译： A / D转换器包括多个子A / D转换器
公开(公告)号：US09559711B2
公开(公告)日：2017-01-31
申请号：US15131969
申请日：2016-04-18
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： Toshiaki Ozeki , Junichi Naka , Takuji Miki
IPC分类号： H03M1/10 , H03M1/12 , H03M1/38
CPC分类号： H03M1/1009 , H03M1/0678 , H03M1/1004 , H03M1/1023 , H03M1/1215 , H03M1/1245 , H03M1/38
摘要： An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N−1) first sampling circuits out of the execution of the calibration.
摘要翻译： A / D转换器包括：输入缓冲器; N个子A / D转换器，包括连接到输入缓冲器的N个第一采样电路，并且对相应采样槽中的输出模拟信号进行采样; 控制电路，一个接一个地执行N个第一采样电路的校准; 参考A / D转换器，包括连接到输入缓冲器的第二采样电路，并且在与N个第一采样之间执行校准的一个第一采样电路的采样时隙相同的采样时隙中对输出模拟信号进行采样电路; 以及连接到输入缓冲器的第三采样电路，并且在与执行校准的第（N-1）个第一采样电路的采样时隙相同的采样时隙中对输出模拟信号进行采样。

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